Paper Title: Applying Design for Test (DFT) to 3D IC Assemblies

Paper Abstract: Designs are scaling in every direction as multiple dies are getting packed and assembled into 2.5D or 3D ICs. Dies or chiplet models must integrate well into a single homogeneous packaged device. Standards such as IEEE 1149.1 (Test Access Port and Boundary-Scan Architecture) and IEEE 1687 (Access and Control of Embedded Instrumentation) can be extended from planar 2D space into 2.5D or 3D ICs. Many current designs are using new standards such as IEEE 1838 (Test Access Architecture in 3D Stacked IC). For 2.5D designs, die-to-die slow speed testing using standard boundary scan-based patterns or at-speed test application using ATPG patterns may suffice. However, new standards such as Universal Chiplet Interface Exchange (UCIe) that come with built-in repair are a must if designers are striving for high yield. Dies or chiplets stacked vertically in a 3D package have their own set of demands to reduce test cost. Testing must be done not only for each individual die at wafer or package level but also for the complete packaged part once assembled. Techniques such as sacrificial (probe) pads to sort the dies may be needed. However, the data gets carried through the first tier of dies in the stack using techniques similar to those used in 2D designs.

Paper Author: Vidya Neerkundar, Product Marketing Manager, Siemens

Author Bio: Vidya Neerkundar is a Product Manager at Siemens EDA where she specializes in DFT. Considered an expert on the subject, she has written an article on it for Semiconductor Engineering magazine and has blogged, presented, and written whitepapers on it. Her current areas of interest are extending DFT to chiplet-based systems and 2.5 and 3D devices, UCIe interfaces, hierarchical DFT, design scaling, and test compression. She has over 20 years experience in DFT. Before joining Siemens EDA, she was an ASIC design engineer for Conexant. She earned an MSEE at Wright State University (Dayton, OH).