Paper Title: Thermal Characterization and Modeling of Heterogeneous Packages

Paper Abstract: Heterogenous integration has become a driving force in semiconductor packaging. The disaggregation of SoCs to multiple chiplets has introduced huge design complexities with thermal design challenges being one of them. The detailed thermal characterization of complex packages with multiple IPs requires the accurate understanding of individual chiplet temperatures and the thermal impedance matrixes describing the cross heating among the components. New methods are necessary to do thermal transient testing for measuring individual chiplet temperatures and the cross-coupling between devices. For each CMOS logic die, the substrate diode method must be used to heat the component and also to capture the volume average temperature of the heated region. A simulation model must then be created and calibrated using the captured data. This allows for accurate simulation of the package, while modeling the exact application conditions.

Paper Author: Andras Vass Varnai, Portfolio Development Executive, Siemens EDA

Author Bio: Andras Vass-Varnai is a Portfolio Development Executive at Siemens EDA, where he focuses on growing US markets. His main areas of interest are thermal management of electrical systems, advanced applications of thermal transient testing, characterization of TIM materials, and reliability testing of high-power semiconductor devices. He earned a PhD in electrical engineering at the Budapest University of Technology and Economics (Hungary). He has over 15 years experience in the EDA business. He has written over 50 publications for such conferences as Electronics Packaging Technology Conference (ECTC), International Conference on Electronics Packaging (ICEP), and the International Workshop on Thermal Investigations of ICs. He also holds four patents.