Paper Title: Moving IC Design from SoC to Chiplet-based SiP

Paper Abstract: Many IC design and verification teams are currently transitioning from monolithic integrated SoC ASIC designs to heterogeneous System-in-Package designs. The new designs must incorporate multiple dies, chiplets, memory dies, chip-to-chip I/O, and memory interface protocols. Front-end design and verification must change a great deal to incorporate the new technologies. There are new requirements for all stages of development: architecture, design, verification, and integration. Also new ways of working between design roles and verification roles are necessary, and new iteration cycles must be introduced, necessitating optimized flows and increased use of automation. Finally, chiplet-based designs require new interface protocols and security features. Design and verification teams must make major changes and adaptations to move the new approach involving 3DIC and chiplets to the mainstream, roll out the new interfaces, and adapt roles to succeed while still meeting demands for ever faster time to market.

Paper Author: Gordon Allan, Product Manager, Siemens EDA

Author Bio: Gordon Allan is Product Manager for Verification IP at Siemens EDA, where he focuses on delivering advanced verification solutions for complex SoC designs. Gordon has had a long career as an SoC design and verification expert. He was a co-author of Accellera’s popular Universal Verification Methodology (UVM), and he published the widely used online UVM Cookbook on the Verification Academy website. Before joining the EDA industry, he spent over 18 years leading and developing SoC and complex protocol IP/VIP projects in semiconductor companies, fabless startups, EDA companies, and system houses. Gordon earned a BSc with honors in computer science from the University of the West of Scotland. He has published eight papers at such conferences as DVcon and ARM TechCon.