Paper Title: Innovative Method for Automated Chiplet Assembly and Physical Verification

Paper Abstract: The chiplet approach to chip design has led to innovation in aspects such as form-factor window, power consumption, total performance, and total cost per solution, but it also has produced new challenges. Many proven approaches are available for combining chiplets into a single working assembly. However, it is still difficult to ensure that all components have been placed correctly in all three dimensions with the proper rotations, transformations, and magnifications to enable the intended electrical behavior properly. It is also difficult to design and verify the power and signal interface connection between the stacked chiplets. An automated approach (based on current EDA tools) to designing chiplet interface, alignment, and placement into a full assembly for final physical verification can help solve the problems.

Paper Author: John Ferguson, Director Product Management, Siemens EDA

Author Bio: John Ferguson is Director of Product Management at Siemens EDA, where he focuses on physical design and verification for design-to-silicon flows. A recognized expert on physical design and verification, he is a frequent author of articles, blogs, and whitepapers and a frequent presenter at conferences and events. He is also the co-author of a chapter of a book on silicon photonics. His current activities include efforts to extend physical verification and design kits enablement for 3DIC design, silicon photonics, quantum computing, and other HPC architectures. He has over 25 years experience in the EDA industry. Ferguson earned a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology. He also holds several patents in design automation. Ehtesham Syed is a Physical Design Engineer at AMD where he works on next-generation chiplet-based SoC products. He leads the physical verification technical team and is responsible for the die level physical verification signoff checks. He was previously an ASIC designer for several years. He earned a BSEE at the University of Toronto, Canada.