Paper Title: Handling Thermo-Mechanical Stress in Chiplets

Paper Abstract: Standard chiplets must allow for use in any environment and with any interposer, as how they are combined into a 2.5D package with other chiplets is not known during design. Silicon interposers are much stiffer than organic substrates and resist bending, so thermally induced expansion of the chiplet can lead to massive shear stresses on the interconnect. This is important because proper distribution of power in a multi-chiplet integrated package can minimize downstream performance issues and reduce the likelihood of design rework. Doing thermo-mechanical analysis early in the design process will lead to a more robust design in a shorter time. An example multi-chip integrated package illustrates how this works in practice. Design choices considered include a silicon interposer and RDL buildup, and chiplet layout with various powering scenarios. Performance implications based on the end-use environment also come in play here.

Paper Author: John Wilson, Business Development Mgr, Siemens EDA

Author Bio: