Paper Title: Chiplet Partitioning Can Balance Among Performance, Flexibility, and Scalability

Paper Abstract: Although chiplet-based designs are now well established in high performance processing, they have yet to be used widely in embedded computing. Embedded applications present special difficulties for chiplets because of stronger constraints on cost, power consumption and interoperability. However, designers can use chiplets effectively in high-performance applications to achieve the right balance among performance, flexibility, and scalability. In particular, dividing the components among heterogeneous computing, physical layers and interconnect can be highly useful. Experience from architectural studies in automotive and embedded applications shows a significant return from applying this approach.

Paper Author: Denis Dutoit, Sr Project Coordinator, CEA-List

Author Bio: Denis Dutoit is a Senior Project Leader in Advanced Computing at CEA-List, one of the world's largest organizations for research in nanotechnology, microelectronics, architecture and system integration. He coordinated the European ExaNoDe project that developed a computer node demonstrator combining chiplets, an active interposer, and bare dies within a System-in-Package (SiP). He has also contributed to the architecture definition of the European Processor Initiative (EPI). His current focus is on architecture pathfinding into chiplet-based designs. Before joining CEA, he was a system-on-chip architect at ST Microelectronics and ST Ericsson. He earned a PhD in signal processing from Telecom Paris, France, in 1988. He has authored or coauthored over 20 articles, including invited talks and tutorials at IEEE-sponsored conferences.