Paper Title: Creating a Sound Die-to-Die Interface for Today's Chiplet-Based Designs

Paper Abstract: Chiplets promise lower costs and faster development for chips at today’s latest process nodes. However, they introduce the need for a high-speed die-to-die interface interconnecting the individual chiplets. The interface increases latency and power consumption, uses extra chip area, and causes signal integrity and test issues. It must also connect properly to the selected package technology, often requiring the latest developments and additional design work. One way to avoid difficulties is by choosing the standard interface and third-party IP that performs the best when benchmarked for a specific application. A proven configurable D2D PHY interface can help considerably by allowing for easy tuning of the system to varied situations.

Paper Author: Letizia Giuliano, VP Solution Engineering, Alphawave SEMI

Author Bio: Letizia Giuliano is VP Solutions Engineering at Alphawave IP, where she is responsible for architecting solutions for SoC customers and technical marketing for high-speed interfaces and chiplet design. She focuses on high-speed connectivity IPs, easy SoC integration, and proactively building new methodologies to accelerate time to market. Before joining Alphawave, Letizia was an IP product line manager at Intel, enabling interface IP for external customers as well as Intel graphics and CPU products. She has also held technical engineering positions at STMicroelectronics with a strong focus on technical marketing, ASIC design, testing, DFT, and failure analysis. Letizia earned an MSEE from Politecnico di Milano. She is a contributor to the OpenHBI specification for a laminate substrate (Open Compute Project).