Paper Title: Developing and Managing System Netlists for Chiplet Integration

Paper Abstract: Chiplet integration must assure both an acceptable yield and correct (as intended) functionality. Assurance, as with standard integrated circuit (IC) designs, depends on the availability of proven and qualified methodologies and workflows that design teams can use to build chiplet products with confidence. As part of physical verification, designers must confirm that the full chiplet assembly (available in a manufacturing format) is connected as expected (as compared to the design intent, which is captured in the system-level design before physical implementation). To run assembly verification, the designer must capture the chiplet assembly connectivity as intended. This can be a challenge as a different design team could own each substrate. A new methodology and process can perform the robust capture and definition of a complete 3D chiplet assemblies netlist which can then be used to drive all downstream verification.

Paper Author: Mike Walsh, Technical Director – IC Packaging Solutions, Siemens

Author Bio: Tarek Ramadan is a senior 3D-IC applications engineer at Siemens EDA. He drives EDA solutions for 2.5D-IC, 3D-IC, and wafer level packaging applications. He focuses on developing software solutions for customer needs. Tarek was previously a technical product manager in the Calibre design solutions organization at Siemens EDA. He earned an MSEE from Ain Shams University, Cairo, Egypt. He has published articles in Semiconductor Engineering magazine, Tech Design Forum, SemiWiki, and Electronics Letters and at IEEE international conferences and Design Automation Conference (DAC).