Paper Title: Integrating Chiplets into Large SiP Systems

Paper Abstract: IC design scaling has historically been accomplished primarily through technology scaling, a process called design-technology co-optimization (DTCO). As pace IC technology scaling has slowed dramatically in recent years, a new process called system technology co-optimization (STCO) is extending design scaling. STCO enables early architectural and technology tradeoffs to achieve high-performance, cost-effective solutions quickly. Predictive analysis is a basic component of STCO that leverages high-level modeling and analysis during planning.

Paper Author: David Ratchkov, CTO and Co-Founder, Anemoi Software

Author Bio: David Ratchkov is the CTO/co-founder of Anemoi Software, a startup which is developing cloud-native thermal analysis tools for solving large, complex design problems. He is also the CEO of Thrace Systems, developer of an integration platform that provides full chip power dissipation analysis throughout the product design and validation cycle. An experienced hardware and software developer, he was previously a Principal Engineer at Broadcom, where he developed power analysis tools. He earned a master’s degree in mathematics and computer science from the University of Plovdiv (Bulgaria). He also leads the Chiplet Design Exchange (CDX) workstream under Open Compute Platform's Open Domain-Specific Architecture (ODSA) sub-project.