Wednesday, January 25th
|B-101: Integration - 1 (sponsored by EMD Electronics) (Partitioning/Integration/Test Track)|
Paper Title: Optimizing Chiplets Using Heterogeneous Integration and Co-Optimization
Paper Abstract: The high costs and lack of flexibility in traditional SoC design have led to a new approach involving heterogeneous integration of functions at the package level. Here a monolithic SoC system is decomposed functionally into smaller chiplets that can be designed separately by dispersed teams or sourced from earlier designs (typically at previous design nodes) or third-party IP. The chiplets can then be combined into a larger highly flexible system with multiple packaging architectures such as 2.5D or 3D and based on silicon or organic based substrates. With such flexibility comes additional challenges such as. chiplet to chiplet interfaces, interconnect optimization, chiplet to package substrate optimization, system-wide power, and thermal and mechanical analysis Dealing with such issues late in the design cycle is expensive and can easily cause schedules to slip. The best way to address them during design is to adopt a System-Technology-Co-Optimization (STCO) methodology and workflow. It provides a system-level view of the chip at all times for reference purposes and to allow for early system-level simulation as chiplets and other features are added. Simulation results can then help design teams make the right decisions early when the cost of change is low.
Paper Author: Per Viklund, Director IC Packaging, Siemens EDA
Author Bio: Per Viklund is Systems Architect Director at Siemens EDA, where he is responsible for IC packaging and RF/microwave technologies. He has been a leader in the development of the Systems Technology Co-Optimization (STCO) methodology for 2.5D and 3D devices. He has over 40 years’ experience with electronic design and EDA and has spent many years focusing on High Density Advanced Packaging (HDAP) and RF/microwave design. He has published multiple papers on RF, IC packaging, and package co-design in journals such as Semiconductor Engineering and at conferences such as the International Conference on Device Packaging.