Paper Title: Warpage Simulation for Assessing Chip-Package Interaction in 3D Stacks

Paper Abstract: A physics-based multi-scale simulation methodology that analyses across die stress variations generated by chip packaging is employed for warpage study. The methodology combines extraction of coordinate-dependent anisotropic effective properties of composite materials with finite element analysis (FEA). It uses the combination to compute mechanical stress components globally on a package-scale, as well as on a feature-scale based on a sub-modeling technique. For the purpose of mechanical failure analysis in the early stage of a package design, the measurements of individual tier warpages were used for the tool’s calibration. The warpage measurements on printed circuit board (PCB), interposer, and chiplet samples, during heating and subsequent cooling, were employed to calibrate the model parameters. The warpage simulation results for a full 3D package represented by a PCB-interposer-chiplets stack demonstrate overall good agreement with the measurement profile. The study confirms that the developed methodology of accurate warpage prediction can be used to optimize IC stack architecture at an early stage of package design.

Paper Author: Junho Choy, Engineer, Siemens EDA

Author Bio: Jun-Ho Choy is an R&D Engineer in the Design to Silicon Division of Siemens EDA. He previously worked at SK Hynix on process development to improve device reliability, and LSI Logic on development of an electromigration simulator. Choy earned a PhD in metallurgical and materials engineering from Michigan Technological University. He has published 26 articles in technical journals such as IEEE Transactions on Computer-Aided Design, Journal Vacuum Science and Technology, and the Journal of Electronic Packaging. He has also published conference presentations in such events as International Symposium on Physical Design (ISPD), International 3D Systems Integration Conference (3DIC), and the IEEE International Reliability Physics Symposium (IRPS).