Tuesday, January 24th
01:00-5:00 PM
Pre-Conference Tutorial G: Test and Integration (Pre-Conference Tutorials Track)
Organizer: Joshua Rubin, Sr Engineer, IBM Research

Paper Title: Incorporating Design-for-Test into the Development of Chiplet-Based Systems

Paper Abstract: Design-for-test techniques have been extended using IEEE 1838 to support multi-die packaging architectures. However, the problem of high-level access remains a concern. How can large volumes of data be moved into and out of chiplet-based products during manufacturing or in the field? In addition, power and thermal issues become even more pronounced as die get stacked in a package. Methods involving the introduction of high-speed component access through standard buses and bandwidth-matching scan access structures are now available to handle the data volume issues. And several techniques, including IEEE 1838 and DFT, can be employed to address power issues and large data volumes.

Paper Author: Adam Cron, Distinguished Architect, Synopsys

Author Bio: Adam Cron is a Distinguished Architect at Synopsys, where he works on test and security tools for digital ICs. Before joining Synopsys, he held test-related positions at Motorola and Texas Instruments. He has helped architect design-for-test, design-for-manufacturing, and security tools for several generations of products. He chairs IEEE 1838 for 3D-IC test access, and is the editor of IEEE P1149.4 for a mixed-signal test bus. He is also chairing a working group to create a Rest API for MITRE's CWE (Common Weakness Enumeration) and CAPEC (Common Attack Pattern Enumeration and Classification) security databases. Adam is an IEEE Golden Core recipient for long-standing service to the society, and has authored several papers and book chapters. He is also a frequent presenter and organizer at conferences such as DAC (Design Automation Conference) and ITC (International Test Conference). He earned a BS in computer engineering from Syracuse University.