Paper Title: Designing a 2000 Chiplet Waferscale Processor

Paper Abstract: As conventional technology scaling becomes harder, 2.5D integration provides a viable pathway to building larger systems at lower cost. Waferscale chiplet-based systems, as much as 100X larger than the largest SoCs, pose new opportunities and challenges in their architecture and design. An example is a 2000 chiplet waferscale processor system, which is 100 times larger than typical chiplet-based devices productized by AMD and NVIDIA. Design difficulties include power delivery, clock distribution, design of area-efficient I/Os, inter-chip network architecture and failure modes, testing strategy, and the uncertainty and constraints of the manufacturing process. Smaller silicon prototypes are currently up and running, and the full waferscale processor is near to completion.

Paper Author: Puneet Gupta, Assistant Professor, UCLA

Author Bio: Puneet Gupta is a Professor in the Electrical and Computer Engineering Department at UCLA, where he focuses his research on design-technology co-optimization and physical design, emerging memory systems, reliability-aware computer architectures, lightweight machine learning systems, and chiplet-based systems and waferscale computing. He has written over 200 papers, holds 18 US patents, and has written a book and a book chapter on design-technology co-optimization. Dr. Gupta has received several faculty awards and is an IEEE Fellow. He was a co-founder and product architect at Blaze DFM, a startup that developed electrical DFM solutions for device manufacturers, fabless semiconductor companies, and silicon foundries. He earned a PhD in Computer Engineering from the University of California at San Diego.