Wednesday, April 27th
2:00 PM-
B-101: Data Center Applications (Edge/Data Center Applications Track)
Paper Title: Building Hardware-Accelerated Networking Applications on SmartNICs

Paper Abstract: It is difficult to process packets deterministically at line speed. Systems that use the host CPU can be interrupted by the operating system or delayed by traffic on a bus. Many SmartNICs include cores that can offload the packet processing from the CPU, but the cores can still experience delays due to cache misses or process scheduling. They can also be subject to security exploits. A new framework architecture builds hardware-accelerated networking applications on SmartNICs with FPGA logic. The framework includes pre-built IP cores that implement ULL Ethernet packet processing, TCP flow processing, and associative lookup. It allows hardware or software developers to customize the data processing using Verilog RTL or C/C++ software compiled to logic using a High Level Synthesis (HLS) compiler. Applications for trading, compliance, and databases have been developed with this framework and deployed on the Cisco V5P SmartNIC, the Xilinx ALVEO, the Intel PAC, Altera DE5Net, and NetFPGA platforms.

Paper Author: John Lockwood, CEO, Algo-Logic
John Hagerman, VP Marketing, Algo-Logic

Author Bio: John Lockwood is the CEO and founder of Algo-Logic Systems, where he develops FPGA-based products that implement network algorithms. Algo-Logic's products lower the latency of automated trading systems, increase the throughput of data center packet processing, accelerate in-memory databases, and process real-time streaming data. Before founding Algo-Logic, he worked at the National Center for Supercomputing Applications (NCSA), AT&T Bell Laboratories, IBM, and SAIC. As a professor at Stanford University, he managed the NetFPGA program and grew it from 10 to 1,021 SmartNIC cards deployed worldwide. He also created and led the Reconfigurable Network Group at Washington University in St. Louis, published over 100 papers and patents on topics related to networking with FPGAs, and was principal investigator on dozens of federal and corporate grants. He earned BS, MS, and PhD degrees in Electrical and Computer Engineering from the University of Illinois at Urbana/Champaign.

Author 2 Bio: