Paper Title: Practical Challenges in Building SmartNICs Using Massively Parallel Cores

Paper Abstract: Developing SmartNICs with a massively parallel architecture presents many challenges. Issues include interconnect, fairness, latency, throughput, and cost. A new approach to the problem involves defining a novel high bandwidth distributed switch fabric to connect thousands of optimized RISC-V cores including multi-die support. Other key innovations are a multi-tiered processing-memory scheme and a programmable cryptographic engine. Programming such an open architecture necessitates a rich development environment with a proven tool chain (including P4 and eBPF support). An example of the proposed software semantics and upstream strategy illustrates the development process.

Paper Author: Steve Zagorianakos, Chief Silicon Architect, Netronome
Johan Tonsing, Chief Architect, Netronome

Author Bio: Steve Zagorianakos is the Chief Silicon Architect at Netronome, where he has led the development of four generations of high performance Network Flow Processors (NFP). He has been responsible for all aspects of silicon development, including product definition and architecture, logic design, pre-silicon verification, emulation, physical implementation, and post-silicon verification. Before joining Netronome, Steve was a silicon architect in the networking division at Intel, where he was responsible for the implementation and microarchitecture of several network processors. Steve holds many patents in processor architecture. He earned a BSEE from the University of Massachusetts Lowell.

Author 2 Bio: