Thursday, April 28th
|A-202: Edge Computing (Edge/Data Center Applications Track)
Paper Title: Advantages and Use Cases for Adding the CXL interface to DPUs
Paper Abstract: Many big data applications require large amounts of memory close to the processor to execute at top speeds. Satisfying such needs with DRAM is difficult because of its cost and high power consumption. For some applications, fixed function accelerators like those found in DPUs also process the data in-situ alongside the main server CPUs. Arm has demonstrated such use cases and built software to execute the in-situ processing functionality on DPUs. Examples show how in-situ processing benefits applications and illustrate how many of them need increased memory capacity directly attached to the DPU to get full value. One way to support such large memory capacities is through new interfaces like CXL which can be leveraged to provision low-cost memory expansion ports on the DPU itself. This approach could provide significant TCO advantages over provisioning memory via the DDR interface. In its coherent (memory-access) mode, CXL offers a high-speed connection specially designed for memory expansion. A CXL connection added to a DPU can provide access to large amounts of high-speed memory at reasonable cost and power levels. Use cases show the advantages of the new approach for a wide range of applications.
Paper Author: Pavel Shamis, Sr Principal Research Engineer, Arm
Author Bio: Pavel Shamis (Pasha) is a Senior Principal Research Engineer at Arm. His work focuses on co-design software, hardware building blocks for high-performance interconnect technologies, development of communications middleware, and novel programming models. Before joining Arm, he was a Research Scientist at Oak Ridge National Laboratory (ORNL) where he worked on high-performance communications domains including Collective Communication Offload (CORE-Direct & Cheetah), OpenSHMEM, and Open Unified Communication X (Open UCX). Before joining ORNL, Pavel worked at Mellanox Technologies, where he led the HPC team and was a key driver in enabling the Mellanox HPC software stack. He holds multiple patents dealing with in-network accelerators. Pavel received a 2015 R&D 100 award for his work on the CORE-Direct in-network computing technology and the 2019 R&D 100 award for developing the Open UCX software framework for HPC, storage, data analytics, and AI.