Paper Title: A Fourth-Generation Architecture for SmartNICs

Paper Abstract: Like most semiconductor devices, SmartNICs have progressed rapidly, leaving older designs (and even older companies) to appear antiquated and ready for a museum shelf somewhere. Advances of particular importance include greater processing power, more flexibility, more support for coprocessors and other hardware devices, programmable packet processing, more cores, scalable fabrics that can handle new hardware implementations such as chiplets, and improved software. So much for today’s wonders with flexible datapaths, performance levels in the range 400-800 Gbps, and DPU capabilities. The next generation will feature many highly-optimized packet-oriented RISC-V cores, a scalable interconnect fabric that can support multiple chiplets, and ready-to-run software for the datapath including upstreamed drivers.

Paper Author: Niel Viljoen, Chief Executive Officer & Founder, Netronome
Jim Finnegan, Sr VP Engineering, Netronome

Author Bio: Niel Viljoen is the founding CEO of Netronome, a leading developer of network processors and SmartNICs. A technology and business visionary, he has led the company in developing X86 networking co-processing solutions, resulting in significant revenue growth. Before founding Netronome, Niel was Group CTO for Marconi and GM/Sr VP of Fore Systems' Service Provider Business Unit, where he drove a highly successful ATM adapter and switch portfolio of products. Niel received his undergraduate degree from the University of Stellenbosch (South Africa) and is a post graduate from Cambridge University (UK).

Author 2 Bio: