Tuesday, April 26th
Tuesday, April 26th
1:00 PM-
Pre-Conference Tutorial A: SmartNIC Basics (Pre-Conference Tutorials Track)
Moderator: Scott Schweitzer, Sr Manager Product Planning, Achronix

Speaker(s):
Presenter: Ash Bhalgat, Sr Director, NVIDIA

Presenter: Motti Beck, Sr Director, NVIDIA

Session Description:
SmartNICs are an important new technology that brings the advantages of edge and distributed technology to today’s networks. They have their own on-board compute elements, which can perform tasks ranging from protocol offload through a variety of systems and applications tasks. They reduce the burden on central processors, allowing them to focus on their primary functions rather than on overhead or work better left to specialty devices. The result is faster, more scalable, and more modular networks better-suited to today’s clouds and data centers. SmartNICs are now available with a variety of architectures. The major difference is in the processing elements. ASIC and FPGA-based devices perform tasks at hardware speeds, but have little flexibility. Processor-based ones are slower but can do almost any task as long as software is available or can be developed. Obviously, software development becomes a major issue. The future of SmartNICs is bright. Most now offload network protocols, thus reducing the overhead that the central processor must handle. Other use cases include storage interfaces, data processing operations such as encryption or compression, media management, AI/ML, virtualization, or security.
About the Organizer/Moderator:
Scott Schweitzer is Sr Manager Product Planning at Achronix Semiconductor, where he helps define SmartNIC and data center accelerator products for FPGAs. He was previously a Technology Evangelist at Xilinx, where he focused on acceleration and helped customers and partners recognize new opportunities and define new innovative solutions. He has also produced the popular blogs TechnologyEvangelist.com and 10GbE.net, which received thousands of monthly page views, and written a series of three articles on SmartNICs for Electronic Design magazine. Before joining Xilinx, Scott worked at SolarFlare Communications, Myricom, NEC Solutions America, and IBM. He earned an MS in Computer Science from NYU’s Tandon School of Engineering.

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Tuesday, April 26th
1:00 PM-
Pre-Conference Tutorial B: Introduction to the P4 Programming Language (Pre-Conference Tutorials Track)
Moderator: Mario Baldi, Fellow, Pensando Systems

Speaker(s):
Presenter: Carmelo Cascone, Sr Staff Engingeer, Intel

Presenter: Mario Baldi, Fellow, Pensando Systems

Presenter: Chris Neely, Research Engineer, AMD

Presenter: Alex Seibulescu, Compiler Development, Pensando Systems

Presenter: Steven Zagorianakos, Chief Silicon Architect, Netronome

Presenter: Deb Chatterjee, Network Acceleration Team Lead, Intel

Session Description:
P4 is a programming language for specifying how network devices such as switches, routers, and NICs process packets. Vendors have used it as the programming language of choice for many products, such as the Cisco Silicon One chipsets, the Barefoot Tofino switches, the Pensando Distributed Services Cards, the AMD SN1000 SmartNIC, and the Aruba CX 10000 smart switch. It is particularly useful for today’s applications that employ software-defined networking (SDN). Using P4 makes network devices easier to program, debug, document, maintain, and update. The main ideas behind P4 are: * Close relationship with typical packet processing tasks. P4 programs specify how packet headers are parsed and what actions are taken based on field values. * Protocol independence: Network devices are not tied to specific protocols. * Target independence: Programmers can describe packet processing for any underlying hardware. * Reconfigurability in the field: Programmers can change the way switches process packets after deployment. The P4 ecosystem includes an extensive range of products, projects, and services. The P4 website (p4.org) is a great source to learn about P4 and join the community. P4’s current tasks include the definition of a Portable NIC Architecture (PNA). Special Feature: Attendees will have opportunities to write P4 code and corresponding control plane functions.
About the Organizer/Moderator:
Mario Baldi is a Fellow at Pensando Systems, where he is in charge of product management for APIs, software development environments, and the third generation system-on-chip. He also participates in the Architecture Workgroup of the P4 community. He was previously Director of Technology at Cisco, where he helped develop the operating system for Nexus switches. He earned a PhD in computer engineering from the Politecnico di Torino (Italy). He has published articles and given presentations on the P4 language and SmartNIC applications.

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Speaker Bio: Chris Neely is a Research Engineer at AMD, where he performs packet processing and SmartNIC-related research. He was previously the Technical Lead for AMD-Xilinx's SDNet packet processing product, which was the first commercial application to support P4_16. He has published eight articles with an emphasis on reconfigurable computing and programmable logic. He holds five patents. His areas of interest include SmartNICs, networking, FPGAs, and embedded systems. He earned a PhD in Computer Engineering from Santa Clara University.

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Tuesday, April 26th
3:15 PM-
Refreshment Break (Pre-Conference Tutorials Track)
Paper Presenters:
Session Description:
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About the Organizer/Moderator:
Tuesday, April 26th
5:00 PM-
Chat with the Experts (Beer/Pizza Expert Table Leaders Event) (Pre-Conference Tutorials Track)
Moderator: Jon Stroud, System Architect, Keysight Technologies

Paper Presenters:
Application Acceleration Table
David McIntyre, Director Product Planning, Samsung Electronics

ASIC-Based Devices Table
Rob Davis, VP Storage, NVIDIA

FPGA-Based Devices
Endric Schubert, CTO, Missing Link Electronics

Testing
Chris Sommers, Software Architect, Keysight Technologies

Security
Brent Cook, Security Director, Stealth Startup

Architectures Table
Andrei Warkentin, ARM Enablement Architect, VMware

DPUs
Frode Nordahl, Sr Engineer, Canonical

Future SmartNIC Features
Scott Schweitzer, Sr Manager Product Planning, Achronix

Networking Applications
Yatish Kumar, R&D Architect, ESnet

Data Center Applications
Venkat Pullela, Chief of Technology Networking, Keysight Technologies

Session Description:
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About the Organizer/Moderator:
Jonathan Stroud is a Senior Systems Architect at Keysight Technologies, where he develops innovative network test and visibility solutions. Before joining Keysight, Jon worked at Breaking Point Systems and Ixia where he focused on RTL based SmartNIC offloads and network processor software to help revolutionize layer 4-7 network application and security testing. He holds three patents in network flow analysis. He studied computer and electrical engineering at North Carolina State University.

Wednesday, April 27th
Wednesday, April 27th
9:00 AM-
Plenary: SmartNICs - Where We Are Today (Plenary Track)
Paper Presenters:
Session Description:
SmartNICs, network interface cards with their own processing power and memory, have quickly become a major growth area in the NIC market. They allow system designers to offload tasks to their on-board processors, reducing the overhead burden on central processing units. Such offload has become important as network speeds increase and protocols become more complex. SmartNICs vary in architecture, with their processing power being implemented in ASICs, FPGAs, network processors, or standard processors. On-board processors obviously require software development, for which many tools (including the P4 networking language) are widely available. Applications have also increased, now including AI/ML, databases, storage tasks, security tasks, and protocol acceleration as well as basic protocol offload. Trends include packaged applications, on-board data or storage processors, special software stacks, and an even wider range of applications, platforms, and tools.
About the Organizer/Moderator:
Wednesday, April 27th
2:00 PM-
A-101: Architectures (Architectures/Software/Tools Track)
Moderator: Itay Ozery, Director Product Management, NVIDIA

Paper Presenters:
Practical Challenges in Building SmartNICs Using Massively Parallel Cores
Steve Zagorianakos, Chief Silicon Architect, Netronome

Johan Tonsing, Chief Architect, Netronome
Upgrading Data Centers with Data Processing Units (DPUs)
Itay Ozery, Director Product Management, NVIDIA

A Fourth-Generation Architecture for SmartNICs
Niel Viljoen, Chief Executive Officer & Founder, Netronome

Jim Finnegan, Sr VP Engineering, Netronome

Session Description:
SmartNIC architectures vary mainly in the implementation of their processing elements. Some use ASICs or FPGAs to achieve high hardware speeds at the cost of imited programmability. Others use general-purpose processors, most often ARM or RISC-V. The result is lower speed, but easier updating or reprogramming. The cost and time consumption of software development is a further issue. Combinations are possible, such as a RISC core included in an ASIC or FPGA or a processor-FPGA pairing, and still others utilize an extended computing unit such as a GPU, a data or storage processor (DPU), a network processor, or an AI chip.
About the Organizer/Moderator:
Itay Ozery is director of product marketing for networking at NVIDIA. He drives strategic product marketing and product management initiatives for data center and cloud networking solutions, with an emphasis on software-defined, hardware-accelerated approaches. Before joining NVIDIA, Itay worked on developing call center software and hardware for NICE Systems. Itay has led large-scale business and projects aimed at IT systems, networking, and cybersecurity for data centers and telecom service providers. He is an active blogger, Webinar presenter, and conference speaker.

Speaker Bio: Niel Viljoen is the founding CEO of Netronome, a leading developer of network processors and SmartNICs. A technology and business visionary, he has led the company in developing X86 networking co-processing solutions, resulting in significant revenue growth. Before founding Netronome, Niel was Group CTO for Marconi and GM/Sr VP of Fore Systems' Service Provider Business Unit, where he drove a highly successful ATM adapter and switch portfolio of products. Niel received his undergraduate degree from the University of Stellenbosch (South Africa) and is a post graduate from Cambridge University (UK).

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Speaker Bio: Steve Zagorianakos is the Chief Silicon Architect at Netronome, where he has led the development of four generations of high performance Network Flow Processors (NFP). He has been responsible for all aspects of silicon development, including product definition and architecture, logic design, pre-silicon verification, emulation, physical implementation, and post-silicon verification. Before joining Netronome, Steve was a silicon architect in the networking division at Intel, where he was responsible for the implementation and microarchitecture of several network processors. Steve holds many patents in processor architecture. He earned a BSEE from the University of Massachusetts Lowell.

Wednesday, April 27th
2:00 PM-
B-101: Data Center Applications (Edge/Data Center Applications Track)
Moderator: Pradeep Sindhu, CEO, Fungible

Paper Presenters:
eFPGAs Bring the Advantages of Programmable Logic to SmartNICs
Ralph Grundler, Sr Director Marketing, Flex-Logix

Handling Data-Centric Workloads with DPU-Based Accelerators
Pradeep Sindhu, CEO, Fungible

Building Hardware-Accelerated Networking Applications on SmartNICs
John Lockwood, CEO, Algo-Logic

John Hagerman, VP Marketing, Algo-Logic

Session Description:
SmartNICs can be useful in a wide variety of data center applications. The most common use case is handling protocol overhead. However, they can also serve other purposes, such as: Encryption/decryption Storage services such as deduplication and mirroring Database or financial functions Security algorithms AI/ML processing Overhead functions such as software-defined storage and virtualization They are particularly well-suited to large clouds, which want to offload overhead activities so they can dedicate processors to chargeable tasks. The high volumes involved here allow manufacturers to provide custom solutions combining circuitry for a cloud’s specific needs with a standard NIC design. An obvious problem is keeping tasks executing on SmartNICs from interfering with each other, an essential feature for cloud applications.
About the Organizer/Moderator:
Satish Kikkeri is Sr Director Product Management at Fungible, a leading maker of data processor units (DPUs). He works on product strategy, definition, roll-out, and go-to-market. He has broad experience across SDN, NFV, NVMe and NVMe-oF, SD-WAN, virtualization, and containers. Before joining Fungible, he was Head of Product Marketing and Product Management for Marvell’s Ethernet Server Adapter Group, where he was responsible for the industry-leading LiquidIO SmartNIC product. He has also worked at Symmetricom and Huawei. He has spoken at conferences and tradeshows worldwide including Gartner Summit, IDC Conference, Cloud Computing World Forum, and Interop. He earned an MBA from the University of Southern California and an MS in computer science from Utah State University.

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Wednesday, April 27th
2:00 PM-
C-101: Panel on Best Way to Program SmartNICs Today (Panels Track)
Moderator: David McIntyre, Director Product Planning, Samsung Electronics

Panel Members:
Panelist: Donglai Dai, Chief Engineer, X-ScaleSolutions

Panelist: Joe White, Fellow, Dell

Panelist: Andrei Warkentin, ARM Enablement Architect, VMware

Panelist: Trevor Caulder, Principal Developer Advocate, NVIDIA

Panelist: Mario Baldi, Fellow, Pensando Systems

Session Description:
Software development is a major issue for SmartNICs, since it often takes a long time and is very expensive. Furthermore, the number of units is not likely to be large enough to allow amortization to have much effect. Also many of the standard operating systems and development environments are available only for X86 processors, not the ARM or RISC-V cores most commonly used in SmartNICs. The addition of other computing elements such as GPUs, DPUs, and AI chips further complicates the process. Developers can counter such problems in various ways, such as using open-source software (for example, the P4 programming language) or commercial modules or IP. Software offers tremendous flexibility, but can cost a bundle even if the latest standard development methods are used.
About the Organizer/Moderator:
David McIntyre is Director Product Planning at Samsung Semiconductor, where he leads product planning and business enablement for computational storage. He focuses on data center cloud to edge acceleration solution in data analytics, security, and AI. He is also a member of the SNIA Computational Storage SIG and a program participant at the Persistent Memory Summit, Flash Memory Summit, and other forums. Before joining Samsung, he worked at Xilinx where he handled new data center initiatives including blockchain. He has also worked at Intel and Altera where he focused on storage, test, and measurement applications for FPGAs. He earned an MSEE from Ohio University and an MBA from San Jose State University.

Wednesday, April 27th
3:10 PM-
A-102: Standards (Architectures/Software/Tools Track)
Moderator: Claudio DeSanti, Distinguished Engineer, Dell

Paper Presenters:
Standardizing SmartNICs for COTS Horizontally-Integrated Solutions
Andrei Warkentin, ARM Enablement Architect, VMware

A Standard API for Accessing Compute Engines on a Network
Pavel Shamis, Sr Principal Research Engineer, Arm

Creating Software That 'Just Works' on SmartNICs
Dong Wei, Standards Architect, Arm

Session Description:
Customers generally want standardization of SmartNICs to avoid dependence on single vendors, allow for universal development tools and platforms, and create a wider and more useful ecosystem. SmartNICs are complex systems, so standards for them will require a lot of work. Standards must cover the basic datapath as well as hardware and software interfaces for applications to use. They must also provide guidelines for writing software that will work on a range of devices and will permit a variety of hardware and software structures, including the use of coprocessors such as DPUs, GPUs, and AI devices. Several standardization efforts are already underway, and a governing body may be needed to coordinate them.
About the Organizer/Moderator:
An experienced architect with a long history in the Internet industry, Claudio DeSanti is a Distinguished Engineer at Dell. He works on technology standardization and evangelization, Ethernet, storage area networks, and open interfaces. He was previously an Architect at Google and a Fellow at Cisco. He is the inventor of FCoE (Fibre Channel over Ethernet) and Chairman of the IEEE P802.3cs “Super-PON” task force. He has presented at many conferences, holds several patents, and is the recipient of four INCITS technical awards. He earned a PhD in computer engineering from Scuola Superiore Sant' Anna (Pisa, Italy).

Wednesday, April 27th
3:10 PM-
B-102: Storage/Security Applications (Edge/Data Center Applications Track)
Moderator: John Kim, Director Storage Marketing, NVIDIA

Paper Presenters:
Five Ways that SmartNICs and DPUs Enhance Cybersecurity
John Kim, Director Storage Marketing, NVIDIA

Session Description:
Storage applications include SAN, NAS, and RAID, as well as standard utilities such as deduplication, encryption/decryption, mirroring, and other functions. SmartNICs can offload tasks from central processors, thus avoiding bottlenecks in networked systems. They can also promote modularity, scalability, and flexibility. Much of the storage management overhead can move to the SmartNICs, thus greatly simplifying the implementation of upgrades, revisions, and new policies. SmartNICs can also be used to implement system-wide views, such as software-defined storage, object storage, or networked filesystems. Security applications include deep packet inspection, firewalls, and defenses against denial-of-service (DDoS) attacks. SmartNICs isolate the security functions for easy updating or replacement, keep threats well away from central facilities, and remove overhead functions so compute units can spend their time doing customer applications.
About the Organizer/Moderator:
John Kim is Director Storage Marketing for NVIDIA’s Networking Division. At NVIDIA, he builds technology solutions and partnerships, researches markets, defines product requirements, and evangelizes new solutions and products to sales, analysts, and customers. Before joining NVIDIA, he worked at Mellanox, EMC, and NetApp. He has been a blogger, a Webinar presenter, and a speaker at SNIA’s Storage Developer Conference. He has over 20 years experience in the storage industry. He earned a Bachelor’s degree from Harvard University.

Wednesday, April 27th
3:10 PM-
C-102: Panel on Next Great Breakthrough in SmartNICs (sponsored by Canonical) (Panels Track)
Session Sponsor: Canonical
Moderator: Endric Schubert, CTO, Missing Link Electronics

Panel Members:
Panelist: Derek Chickles, Director Machine Learning, Marvell

Panelist: Manoj Roge, HPC / Data Center Segment Lead, Synopsys

Panelist: Rob Davis, VP Storage, NVIDIA

Panelist: Frode Nordahl, Sr Engineer, Canonical

Panelist: Ahmet Houssein, CEO, SiPanda

Session Description:
Many important changes will surely occur in the emerging SmartNIC arena. They include the addition of standard slots for GPUs and DPUs, faster processors, more canned applications (perhaps available via an app store), more standards, and greater use of processors other than standard ARM cores. Other possible advances could include the integration of on-board optics, higher frequency versions of Ethernet, the use of persistent memory, and the use of higher-speed interfaces such as CXL.
About the Organizer/Moderator:
Endric Schubert is an experienced technologist and entrepreneur in electronic and semiconductor design. He is currently CTO at Missing Link Electronics, which specializes in FPGA-based acceleration for networking, communications, and storage applications. His background includes software engineering, FPGA technology, reconfigurable computing, and embedded systems design. He has extensive experience in FPGA-based design, ASIC development, IP creation, and software development. He has authored technical publications, holds several patents, and has given lectures on electronic system design. Endric earned an Electrical Engineering degree (Dipl.-Ing.) from University of Karlsruhe, Germany and a PhD in computer science from the University of Tubingen, Germany.

Wednesday, April 27th
4:20 PM-
A-103: Development Tools/Platforms (Architectures/Software/Tools Track)
Moderator: Jim Ballingall, Executive Director, Industry-Academia Partnership

Paper Presenters:
Simplifying Infrastructure Offload and Management on SmartNICs
Kyle Mestery, Sr Principal Engineer, Intel

Choosing a Platform for FPGA-Based In-Network Compute Acceleration
Endric Schubert, CTO, Missing Link Electronics

Ulrich Langenbach, Director Engineering, Missing Link Electronics
Developing Software for Data Center Infrastructure Applications
Deb Chatterjee, Network Acceleration Team Lead, Intel

Session Description:
There are many development platforms already available for SmartNICs. Manufacturers often supply one, and others are available from open-source projects or software vendors. Developers should pick a platform that supports many SmartNICs, is easy to use, and has a large ecosystem of tools and other support. An open-source platform is often a good first choice when developers are uncertain as to how to proceed. Many open-source tools and utilities are also available, including ones created in university environments.
About the Organizer/Moderator:
Jim Ballingall is the Executive Director of the Industry-Academia Partnership (IAP), an association dedicated to advancing cloud technologies to meet the demands of data centers and their customers. It focuses on both applications and infrastructure , bringing together industry and university partners on issues such as AI/ML, hardware acceleration, operating systems, networking, big data, security, storage, and data management. Before joining IAP, Jim was VP Global Marketing at GlobalFoundries, a leading worldwide semiconductor fab. He has over 25 years experience in the semiconductor industry. He earned a PhD in applied physics from Cornell University and a BS in engineering physics from UC Berkeley.

Wednesday, April 27th
4:20 PM-
B-103: High-Performance Computing (Edge/Data Center Applications Track)
Moderator: Addison Snell, CEO, Intersect360 Research

Paper Presenters:
A SmartNIC Developed for Scientific Applications
Yatish Kumar, R&D Architect, ESnet

Accelerating HPC Applications with SmartNICs
Donglai Dai, Chief Engineer, X-ScaleSolutions

Session Description:
High-performance computing is an obvious application for SmartNICs. HPC practitioners are always looking for more performance at relatively low cost. Offloading overhead functions to SmartNICs allow expensive compute units to spend their time doing useful work. Network protocol handling, message-passing, security, and utilities such as encryption/decryption, compression/decompression, and error handling are among the typical tasks often turned over to relatively inexpensive SmartNICs. Besides, new supercomputers don’t come along very often, so one needs to get all the performance possible from current hardware.
About the Organizer/Moderator:
Addison Snell is the CEO of Intersect360 Research and a veteran of the high performance computing (HPC) industry. He has established Intersect360 Research as a premier source of market information, analysis, and consulting. He was named one of 2010's "People to Watch" by HPCwire. He is a regular participant at both Supercomputing and the ISC High-Performance conferences as a speaker, panelist, and chairperson. Before co-founding Intersect360, Addison was an HPC industry analyst for IDC, where he was well-known among industry stakeholders. Before joining IDC, he was a marketing leader and spokesperson for SGI's supercomputing products and strategy. Addison holds a master's degree from the Kellogg School of Management at Northwestern University and a bachelor's degree from the University of Pennsylvania.

Wednesday, April 27th
4:20 PM-
C-103: Panel on Optimizing SmartNIC Applications (sponsored by Napatech) (Panels Track)
Moderator: Leonid Grossman, Director, NVIDIA

Panel Members:
Panelist: Vikram Singh, Sr Product Line Manager, Juniper Networks

Panelist: Jarrod J.S. Siket, CMO, Napatech

Panelist: Rong Pan, Fellow, Intel

Panelist: Prasun Kapoor, Sr Director of Software Engineering, Marvell

Panelist: Nabil Damouny, Principal, Autonomous Edge

Session Description:
The usual issue is to get applications to run faster. One common problem is a slow network stack, so check around to see if yours is the latest version or team members or associates have found others to be more efficient. Other common approaches include replacing the processor with a faster model – some SmartNICs have chips that are way behind the state-of-the-art. Still other alternatives are replacing or upgrading the message passing mechanism that starts up the SmartNIC and moves its results – everything may be delayed if messages are not being generated or recognized efficiently. Some NICs even have internal features that offload or speed up message processing. Other system software may also run much faster if it executes at the network level rather than the host level. There are even tools available that can predict how large a performance gain you can expect from offloading.
About the Organizer/Moderator:
Leonid Grossman is Director of Cloud Network Engineering at NVIDIA, where he works on a private cloud that involves large numbers of SmartNICs. Before joining NVIDIA, he was Director Software Development at Oracle where he delivered the networking roadmap for Oracle Solaris and led its integration with the public cloud. He also represented Oracle in the Open Networking Foundation and the OpenDaylight SDN Project team. He previously worked on 10GbE networking software at Neterion, where he was a co-founder and VP Software Engineering. He earned a Master’s degree in computer science from the Moscow Institute of Physics and Technology.

Thursday, April 28th
Thursday, April 28th
9:00 AM-
A-201: System Development (Architectures/Software/Tools Track)
Moderator: Andrei Warkentin, ARM Enablement Architect, VMware

Paper Presenters:
Simplifying SmartNIC System Testing
Razvan Stan, Sr Engineering Manager, Keysight Technologies

Leveraging P4 in SmartNICs: Expected Benefits, Challenges, and Solutions
Mario Baldi, Fellow, Pensando Systems

Session Description:
System development for SmartNICs is a difficult process. Developers for any new technology always face a lack of widely available, mature platforms. Such platforms usually include a wide range of tools such as programming languages and test tools. Open-source projects provide further examples. However, it is generally up to the development team to find the tools and make them work together for stages from problem definition through debug and test.
About the Organizer/Moderator:
Andrei Warkentin is an Arm Enablement Architect at VMware, where he is the Technical Lead for the ESXi-ARM team which conducts advanced development of vSphere hypervisor technology for the 64-bit Arm architecture. He is an architect for Project Monterey, an extension of VMware Cloud Foundation (VCF) using SmartNICs to improve performance, implement zero-trust security, and simplify operations across data center, edge, and cloud applications. He has worked on a wide range of issues related to Arm enablement and strategy, ranging from low-level hypervisor design and implementation to product definition and partner and ecosystem engagement. Before joining VMware, he worked at Motorola Mobility on Google Experience devices and at Microsoft on Hyper-V and UEFI projects. He earned a BS in computer science from the University of Illinois Chicago. He holds 38 patents and has three publications.

Thursday, April 28th
9:00 AM-
B-201: Open Networking (Edge/Data Center Applications Track)
Moderator: Nabil Damouny, Principal, Autonomous Edge

Paper Presenters:
Extending DPUs to Enable Software-Defined I/O (SDIO)
Dhaval Parikh, Director Segment Marketing, Arm

DPUs in Open Infrastructure Deployments
Frode Nordahl, Sr Engineer, Canonical

Dmitry Shcherbakov, Sr Engineer, Canonical

Session Description:
Open networking approaches are an obvious foundation on which to develop SmartNIC applications. They provide ways to define infrastructure in software rather than in hard-to-change and usually proprietary hardware. However, such approaches often create a lot of management overhead that can slow down systems significantly. Data processing units (DPUs) are a new way to handle the overhead without causing system saturation, keeping it totally away from central processors. New approaches and new software versions also become much easier to implement.
About the Organizer/Moderator:
Nabil Damouny is the Principal at Autonomous Edge Consulting, where he focuses on edge applications using SmartNICs in a wide variety of areas. He was previously Sr Director of Strategic Marketing at Netronome, where he worked on marketing and business development opportunities in networking, storage, and high-performance computing. He has also been a founder and VP Marketing at Basis Communications, a maker of network processors which was acquired by Intel. Earlier he worked at Intel in the CTO office of the Mobility Group. He has published over 25 technical and marketing papers, and is a frequent speaker at conferences. He took active part in many standard committees including ATM Forum, FDDI, IEEE802, IETF, and ISDN. Nabil earned a BSEE from IIT in Chicago, and an MSECE from UC Santa Barbara. He holds three patents in computer architecture and remote networking.

Thursday, April 28th
9:00 AM-
C-201: Panel on Best Architecture for SmartNICs Today (sponsored by Marvell) (Panels Track)
Session Sponsor: Marvell
Moderator: Jim Harrison, Editor-in-Chief, Lincoln Technology Communications

Panel Members:
Panelist: Derek Chickles, Director Machine Learning, Marvell

Panelist: Jim Finnegan, Sr VP Engineering, Netronome

Panelist: John Lockwood, CEO, Algo-Logic

Panelist: Wael Noureddine, Chief Architect, Fungible

Panelist: Rob Davis, VP Storage, NVIDIA

Session Description:
Current SmartNIC architectures offer many tradeoffs. Ones based on ASICs or FPGAs are generally faster and easier to implement. Those based on standard processors are more flexible and easier to update. Coprocessors such as GPUs or DPUs increase performance but are expensive and difficult to program. Most observers expect the software-based devices to dominate the market because of their flexibility, but performance issues could leave a substantial market for hardware-based SmartNICs. The cost and time requirements for developing typical applications for processor-based SmartNICs is as yet unknown, but could have a big effect.
About the Organizer/Moderator:
Jim Harrison is the Editor-in-Chief at Lincoln Technology Communications and the author of many papers for numerous technology companies covering design of electronic systems and devices and providing interesting content on electronic components. He has written about everything from the latest gadgets to in-depth circuit design ideas. He spent 12 years as West Coast Editor for Electronic Products Magazine, where he covered a broad spectrum of technology ranging from ICs to passive components and design tools. Before that, he was an engineer for networking and telecom companies.

Thursday, April 28th
2:30 PM-
A-202: Edge Computing (Edge/Data Center Applications Track)
Moderator: Nabil Damouny, Principal, Autonomous Edge

Paper Presenters:
DPUs Help Systems Process Huge Data
Guru Bachchu, Lead Applications Engineer, Kalray

Advantages and Use Cases for Adding the CXL interface to DPUs
Pavel Shamis, Sr Principal Research Engineer, Arm

SmartNIC Architecture for Distributed Services at the Network Edge
Mario Baldi, Fellow, Pensando Systems

Session Description:
Edge computing means that a great deal of required processing occurs at the system edge, near where the data enters and leaves the system. The result is less traffic on buses and smaller burden on central compute units. However, such approaches do require extensive development of applications, high-speed interfaces at the edge, and often special chips such as DPUs that take over routine tasks. Programs and data must be provided to the edge processors, and results must be obtained from them. This all requires a communications system that is robust, fast, and easy-to-use.
About the Organizer/Moderator:
Nabil Damouny is the Principal at Autonomous Edge Consulting, where he focuses on edge applications using SmartNICs in a wide variety of areas. He was previously Sr Director of Strategic Marketing at Netronome, where he worked on marketing and business development opportunities in networking, storage, and high-performance computing. He has also been a founder and VP Marketing at Basis Communications, a maker of network processors which was acquired by Intel. Earlier he worked at Intel in the CTO office of the Mobility Group. He has published over 25 technical and marketing papers, and is a frequent speaker at conferences. He took active part in many standard committees including ATM Forum, FDDI, IEEE802, IETF, and ISDN. Nabil earned a BSEE from IIT in Chicago, and an MSECE from UC Santa Barbara. He holds three patents in computer architecture and remote networking.

Thursday, April 28th
2:30 PM-
B-202: Panel on SmartNIC Standards: What Is Needed Today?(sponsored by Keysight) (Panels Track)
Session Sponsor: Keysight Technologies
Moderator: Kimball Brown, Analyst, Analyst

Panel Members:
Panelist: Dong Wei, Standards Architect, Arm

Panelist: Joe White, Fellow, Dell

Panelist: Venkat Pullela, Chief of Technology, Keysight Technologies

Panelist: Vipin Jain, CTO, Pensando Systems

Session Description:
SmartNICs are currently not standardized at all. Each vendor has its own architectures, programming methods, and APIs. Obviously, customers have a difficult time deciding what they need and determining a clear path forward. What steps must be taken to improve the situation without limiting options or forcing choices before there is enough evidence to proceed? Is a new organization necessary or is it better to work within an existing one to reduce overhead costs? Several frameworks have already been suggested by vendors and academic researchers. Where do they fit into the picture?
About the Organizer/Moderator:
Kimball Brown is a Senior Alliances Advisor for the security software firm BlackRidge Technology. He was previously a Global Technical Strategist at VMware, where he engaged Cisco in co-development projects. He has also been a VP/Sr Datacom Analyst with LightCounting, a specialist group focused on high-speed interfaces and communications devices. He has experience with Broadcom and Dataquest as well. He earned an MBA from UC Berkeley and a BSEE from Duke University.

Thursday, April 28th
2:30 PM-
C-202: Academic Session (Academic Track)
Moderator: Ming Liu, Assistant Professor, University of Wisconsin - Madison

Paper Presenters:
NanoPU: A Nanosecond Network Stack for Data Centers
Stephen Ibanez, Researcher, Intel

Gimbal: Enabling Multi-tenant Storage Disaggregation on SmartNIC JBOFs
Jaehong Min, Graduate Student, University of Washington

FlexTOE: Flexible TCP Offload with Fine-Grained Parallelism
Rajath Shashidhara, Graduate Student, University of Washington

PANIC: A High-Performance NIC for Multi-Tenant Networks
Jiaxin Lin, Graduate Student, University of Texas - Austin

Session Description:
Academic research in SmartNICs has progressed rapidly in the past few years. There are many interesting contributions in the following general areas: . Architectures . Transport . Application Services . Programming Language Support Industry will surely find many of these projects to be of immediate interest to them for both ideas and personnel.
About the Organizer/Moderator:
Ming Liu is an Assistant Professor in the Computer Sciences Department at the University of Wisconsin – Madison. His research covers networking and systems, with a focus on network-based hardware acceleration. His projects include NVMe-oF targets for SmartNIC JBOFs, using SmartNICs to accelerate distributed transaction processing and offload actor-based distributed applications, and developing automated offloading insight for SmartNICs and using a data-flow based programing system for developing SmartNIC applications. He earned his PhD at the University of Washington and was a postdoctoral researcher at VMware. He has 11 published conference papers.

Thursday, April 28th
4:00 PM-
A-203: DPU's (Architectures/Software/Tools Track)
Moderator: Dong Wei, Standards Architect, Arm

Paper Presenters:
Server Networking Solutions Using DPUs
John Kim, Director Storage Marketing, NVIDIA

Offloading Networking and Security Overhead to Nearby DPUs
Vikram Singh, Sr Product Line Manager, Juniper Networks

Session Description:
DPUs can take over many time-consuming tasks in networked systems, thus reducing bus traffic and burdens on central processors. DPUs can be located near the network’s edge, thus putting them directly in the path between the network and central computing facilities. Such approaches also make processing easy to change or upgrade, requiring only changes in the DPU software.
About the Organizer/Moderator:
Dong Wei is a Lead Standards Architect and Fellow at Arm. He leads the Arm SystemReady Program. He has significant experience in leading the industry in innovations and standardization. He is the Vice President (Chief Executive) of the UEFI Forum and co-chairs its ACPI Working Group. He is a Board member of the PCI SIG and co-chairs its Firmware Working Group. He is a Board member and the Secretary of the CXL Consortium. He is a member of the Incubation Committee at the OCP Foundation. He is a Senior Member of IEEE. Before joining Arm, Wei was VP/Fellow at Hewlett-Packard and Hewlett Packard Enterprise (HPE). As the Chief Architect for UEFI and ACPI, he led the definitions of the interfaces of hardware, firmware, and operating systems for x64, x86, Arm, ia64, RISC-V and PA-RISC based systems. He earned an MSEE from the University of Idaho and an MBA from California State University - Sacramento. He has five published articles.

Thursday, April 28th
4:00 PM-
B-203: Panel on SmartNICs in 2027 & How We Got There (sponsored by X-Scale) (Panels Track)
Session Sponsor: X-ScaleSolutions
Moderator: Jim Finnegan, Sr VP Engineering, Netronome

Panel Members:
Panelist: Manoj Roge, HPC / Data Center Segment Lead, Synopsys

Panelist: Scott Schweitzer, Sr Manager Product Planning, Achronix

Panelist: Baron Fung, Director, Dell'Oro Group

Panelist: DK Panda, Professor, Ohio State University

Session Description:
The five-year horizon for SmartNICs is very promising. They will make up an ever increasing part of the NIC market, as their cost is more than balanced by the tremendous capabilities they bring to networked systems. More canned software will be available for them, as well as development platforms, operating systems, utilities, and other tools. Standardization will be a major issue, as most large customers will want multiple sources as well as large ecosystems and wide support for both development and test. Other issues include achieving higher throughput and lower latency, isolating executing applications from one another, security, and operating system support.
About the Organizer/Moderator:
Jim Finnegan is COO at Netronome, a maker of network processors and SmartNICs. Before joining Netronome, he worked at Intel, where he was general manager of both the Network Processor Division and the Communication Infrastructure Group's Technology Office. He has over 30 years' experience in the networks and communications businesses, including positions at Digital Equipment and Tellabs. He earned Bachelor's and Master's degrees in electronic engineering from Queen's University Belfast (Northern Ireland).