Wednesday, June 14th
SmartNICs: Where We Are Today (sponsored by Synogate) (Plenary Track)
Plenary Intro - Click for Proceedings
Chuck Sobey, General Chair, SmartNICs Summit

SmartNICs Market Update - Click for Proceedings
Baron Fung, Research Director, Dell'Oro Group

State of SmartNICs Today - Click for Proceedings
Scott Schweitzer, Director SmartNIC Product Planning, Achronix

A-101: Networking Applications 1 – Communications Issues (Networking Track)
Using SONiC-DASH to Create Ultra-High-Speed Cloud Switches
Reshma Sudarshan, Director of Applications Engineering, Intel

Generating Packets with SmartNICs and the P4 Language
Marcin Parafiniuk, Sr Software Engineer, CodiLime

B-101: Data Center Applications (Data Centers Track)
Offload More Functions to DPUs Using On-Board Low-Power Cores
Matthew Dirba, Staff Design Engineer, Arm

SmartNICs/DPUs Save Millions in Data Center Power Costs
John Kim, Director Storage Marketing, NVIDIA

C-101 Best Way to Program SmartNICs Today Panel (Panels Track)
C-101 Panel Ozery - Click for ProceedingsC-101 Panel Jain - Click for ProceedingsC-101 Panel Wrobel - Click for ProceedingsC-101 Panel Lockwood - Click for Proceedings
Panel Members:
Panelist: Itay Ozery, Director Product Management, NVIDIA

Panelist: Vipin Jain, Sr Fellow Engineer, AMD

Panelist: Krzysztof Wrobel, Director Engineering, CodiLime

A-102: Networking Applications 1 - Telco Networks (Networking Track)
Using SmartNICs to Accelerate Network Function Virtualization (NFV)
Geetha Jayagopi, Strategic Planner, Intel

Mirek Walukiewicz, Solution Architect, Intel
Using SmartNICs in 5G Networks
Awanish Verma, Director/Principal Architect, AMD

B-102: Storage/Security Applications (Data Centers Track)
Protecting SmartNICs with Physical Unclonable Functions (PUFs) - Click for Proceedings
Reed Hinkel, VP Business Development, Intrinsic ID

Implementing High-Speed Storage Solutions with SmartNICs and DPUs - Click for Proceedings
Rob Davis, VP Storage, NVIDIA

DPUs and AI Protecting Legacy Storage Servers - Click for Proceedings
Michael Brew, Technical Specialist, BloomBase

C-102: Next Great Breakthrough in SmartNICs Panel (sponsored by Canonical) (Panels Track)
Panel Members:
Panelist: Jon Sreekanth, Architect, Achronix

Panelist: Eric Hibbard, Director Product Planning - Security, Samsung Semiconductor

Panelist: Frode Nordahl, Sr Engineer, Canonical

A-103: Network Acceleration 2 - System Applications (Networking Track)
Removing the Tail from SmartNIC Latency - Click for Proceedings
John Lockwood, CEO, Algo-Logic

High-Speed Secure Virtual Application Delivery Using FPGA-Based SmartNICs - Click for Proceedings
Tim Michels, Distinguished Engineer, F5 Networks

Geetha Jayagopi, Strategic Planner, Intel
Using a SmartNIC to Recover Dropped Packets - Click for Proceedings
Paul Borrill, CEO, Daedaelus

B-103: Software 1 - Operating Systems (Software Track)
Highly Secure OS Kernel for SmartNIC Applications
Pawel Duleba, Sr Software Engineer, CodiLime

Provisioning and Commissioning a DPU at the Bare-Metal Level
Bjorn Tillenius, Software Engineer, Canonical

Frode Nordahl, Sr Engineer, Canonical

C-103: Optimizing SmartNIC Applications Panel (sponsored by Keysight) (Panels Track)
Panel Members:
Panelist: T Sridhar, VP Architecture, Juniper Networks

Panelist: Venkat Pullela, Chief Of Technology, Networking, Keysight Technologies

Panelist: Scott Schweitzer, Director SmartNIC Product Planning, Achronix

Panelist: Donglai Dai, Chief Engineer, X-ScaleSolutions

Panelist: Andy Fingerhut, Principal Engineer, Intel