Wednesday, April 27th
Plenary: SmartNICs - Where We Are Today (Plenary Track)
A-101: Architectures (Architectures/Software/Tools Track)
Practical Challenges in Building SmartNICs Using Massively Parallel Cores - Click for Proceedings
Steve Zagorianakos, Chief Silicon Architect, Netronome

Johan Tonsing, Chief Architect, Netronome
Upgrading Data Centers with Data Processing Units (DPUs)
Itay Ozery, Director Product Management, NVIDIA

A Fourth-Generation Architecture for SmartNICs - Click for Proceedings
Niel Viljoen, Chief Executive Officer & Founder, Netronome

Jim Finnegan, Sr VP Engineering, Netronome

B-101: Data Center Applications (Edge/Data Center Applications Track)
eFPGAs Bring the Advantages of Programmable Logic to SmartNICs - Click for Proceedings
Ralph Grundler, Sr Director Marketing, Flex-Logix

Handling Data-Centric Workloads with DPU-Based Accelerators
Pradeep Sindhu, CEO, Fungible

Building Hardware-Accelerated Networking Applications on SmartNICs - Click for Proceedings
John Lockwood, CEO, Algo-Logic

John Hagerman, VP Marketing, Algo-Logic

C-101: Panel on Best Way to Program SmartNICs Today (Panels Track)
C-101 Panel Presentation - Click for Proceedings
Panel Members:
Panelist: Donglai Dai, Chief Engineer, X-ScaleSolutions

Panelist: Mario Baldi, Fellow, Pensando Systems

Panelist: Andrei Warkentin, ARM Enablement Architect, VMware

Panelist: Joe White, Fellow, Dell

Panelist: Trevor Caulder, Principal Developer Advocate, NVIDIA

A-102: Standards (Architectures/Software/Tools Track)
Standardizing SmartNICs for COTS Horizontally-Integrated Solutions - Click for Proceedings
Andrei Warkentin, ARM Enablement Architect, VMware

A Standard API for Accessing Compute Engines on a Network - Click for Proceedings
Pavel Shamis, Sr Principal Research Engineer, Arm

Creating Software That 'Just Works' on SmartNICs - Click for Proceedings
Dong Wei, Standards Architect, Arm

B-102: Storage/Security Applications (Edge/Data Center Applications Track)
Five Ways that SmartNICs and DPUs Enhance Cybersecurity - Click for Proceedings
John Kim, Director Storage Marketing, NVIDIA

C-102: Panel on Next Great Breakthrough in SmartNICs (sponsored by Canonical) (Panels Track)
Panel Members:
Panelist: Derek Chickles, Director Machine Learning, Marvell

Panelist: Manoj Roge, HPC / Data Center Segment Lead, Synopsys

Panelist: Rob Davis, VP Storage, NVIDIA

Panelist: Ahmet Houssein, CEO, SiPanda

Panelist: Frode Nordahl, Sr Engineer, Canonical

A-103: Development Tools/Platforms (Architectures/Software/Tools Track)
Choosing a Platform for FPGA-Based In-Network Compute Acceleration - Click for Proceedings
Endric Schubert, CTO, Missing Link Electronics

Ulrich Langenbach, Director Engineering, Missing Link Electronics
Simplifying Infrastructure Offload and Management on SmartNICs - Click for Proceedings
Kyle Mestery, Sr Principal Engineer, Intel

Developing Software for Data Center Infrastructure Applications - Click for Proceedings
Deb Chatterjee, Network Acceleration Team Lead, Intel

B-103: High-Performance Computing (Edge/Data Center Applications Track)
A SmartNIC Developed for Scientific Applications
Yatish Kumar, R&D Architect, ESnet

Accelerating HPC Applications with SmartNICs - Click for Proceedings
Donglai Dai, Chief Engineer, X-ScaleSolutions

C-103: Panel on Optimizing SmartNIC Applications (sponsored by Napatech) (Panels Track)
C-103 Panel Presentation - Click for Proceedings
Panel Members:
Panelist: Vikram Singh, Sr Product Line Manager, Juniper Networks

Panelist: Rong Pan, Fellow, Intel

Panelist: Jarrod J.S. Siket, CMO, Napatech

Panelist: Prasun Kapoor, Sr Director of Software Engineering, Marvell

Panelist: Nabil Damouny, Principal, Autonomous Edge