Thursday, January 23rd
A-201: Design - 3 (Design/Security Track)
Unlocking XPU Performance with Chiplets
Michael Klempa, Product Marketing Engineer, Alphawave Semi

Ilamparidhi I, Principal SI/PI, Alphawave Semi
New Platform for System Level Validation of Chiplet Based Designs - Click for Proceedings
Luis E. Rodriguez, Senior Technical Product Manager, Siemens

TziYang Shao, Product Lead, Siemens

B-201: Integration - 1 (Interfaces & Integrations Track)
Fast-Track Chiplet Integration with UCIe Electrical Layer Analysis - Click for Proceedings
Tim Wang Lee, Signal Integrity Application Scientist, Keysight Technologies

Performing Multiphysics Analysis During Heterogeneous Integration
Tarek Ramadan, Applications Engineering Manager, 3D-IC, Technical Solutions Sales, Siemens

Mike Walsh, Applications Engineering Manager, 3D-IC, Technical Solutions Sales, Siemens
Mahmoud Farid, , Siemens

C-201: Making Chiplets a Viable Market (sponsored by Credo) (Panel Track)
Panel Members:
Panelist: Letizia Giuliano, VP Solutions Engineering, Alphawave Semi

Panelist: Jeff Twombly, VP Business Development, Credo

Panelist: Scott Knowlton, Sr Director - Multi-Die, Synopsys

Panelist: Amber Huffman, Lead Technologist, Google

Panelist: Gerald Pasdast, Sr Principal Engineer, Intel

Panelist: Ravi Agarwal, Director Technology Pathfinding, Meta

D-201: Annual Update on Accelerating Generative AI (Annual Update Track)
B-202: Interfaces - 3 (Interfaces & Integrations Track)
Using HBM (High Bandwidth Memory) in AI Acceleration
Soni Kapoor, Product Marketing Manager, Alphawave Semi

Tiled Approach to System Scaling - Click for Proceedings
Guillaume Boillet, Sr Director Product Management, Arteris IP

Achieving Higher Bandwidth with HBM4 for Demanding Workloads
Raj Uppala, Senior Director of Marketing & Partnerships, Rambus

Kevin Yee, Sr. Directory of Foundry Marketing, Samsung Semiconductor

C-202: Chiplets for Entrepreneurs - Making Money in the Chiplet Game (Panel) (Panel Track)
Panel Members:
Panelist: Laura Swan, Managing Partner, Silicon Catalyst Ventures

Panelist: Blair Georgakas, Investment Manager, Applied Ventures

Panelist: Helen Li, Managing Director, Needham

Panelist: Kash Johal, CEO, YorChip

D-202: Interfaces - 4 (UCIe Version 2.0) (Interfaces & Integrations Track)
UCIe Layered Approach to Die-to-Die Interface
Gerald Pasdast, Sr Principal Engineer, Intel

UCIe Offers Lower Power and Higher Performance via 3D Interconnect
Zuoguo (Joe) Wu, Electrical Working Group Co-Chair, UCIe Consortium

UCIe Offers Flexible Manageability and Security
Jerome Glisse, Software Engineer, Google

B-203: Chiplets in 2030 and How We Got There (Panel) (Panel Track)
Panel Members:
Panelist: Bill Mullen, Fellow, Ansys

Panelist: Bapi Vinnakota, Project Manager, National Advanced Packaging Manufacturing Program (NAPMP)

Panelist: Laura Swan, Managing Partner, Silicon Catalyst Ventures

Panelist: Tom Hackenberg, Principal Analyst, Yole Group

Panelist: Brucek Khailany, Sr Director VLSI Research, NVIDIA