Wednesday, January 22nd
Chiplets: Where We Are Today (sponsored by Applied Materials) (Plenary Track)
The Chiplet Market Today and Where We’re Headed - Click for Proceedings
Jim Handy, Analyst, Objective Analysis

Got a Lot of Chip Designin' to Do - Click for Proceedings
Jawad Nasrullah, CEO, Palo Alto Electron

A-101: Security - 1 (Design/Security Track)
Simple Solution for Certifying Chiplet Origin
Richard Beaudry, CEO, Digitho

Efficiently Address Side-Channel Leakage Using Pre-Silicon Simulation
Nicole Fern, Principal Security Analyst, Keysight Technologies

Security Solutions for Multi-Die Designs
Dana Neustadter, Senior Director of Product Management, Synopsys

Multi-Layered Security for Chiplet Testing
Lee Harrison, Marketing Director, Siemens

B-101: Interfaces - 1 (Interfaces & Integrations Track)
Chiplet Interconnect Test and Repair Using Test Standards - Click for Proceedings
Anshuman Chandra, Lead R&D for 3D/2.5D Devices, Siemens

Martin Keim, Product Manager, Siemens
Interface IP Requirements for AI Applications and 3D Packaging Technologies - Click for Proceedings
Manuel Mota, Sr. Product Manager, Synopsys

C-101: Creating Foundry-Ready Chiplet Designs Panel (sponsored by Chroma ATE) (Panel Track)
Panel Members:
Panelist: Boris Vaisband, Assistant Professor, UC Irvine

Panelist: Kenneth Larsen, Director Product Marketing, Synopsys

Panelist: Anup Suggula, Chief Engineer, AMD

Panelist: Pavel Rott, Partner, Mueon

D-101: Next Great Breakthrough in Chiplets (Panel Track)
E-101: Annual Update on Packaging (Packaging Track)
Advanced Packaging: Key Enabler for Next Generation HPC and AI Architectures
Chandra Mandalapu, Sr Member Technical Staff, AMD

A-102: Design - 1 (Design/Security Track)
Accelerate Time-to-Market Using a Hub and FPGA Chiplets - Click for Proceedings
Nick Ilyadis, VP Product Planning, Achronix

Il (Will) Park, CEO, PRIMEMAS
Creating Compute Chiplets for Rapid Automotive SoC Deployment
Darryl Koivisto, CTO, MIRABILIS DESIGN

Using AI to Improve EDA Tools for Multi-Die Architectures - Click for Proceedings
Sutirtha Kabir, R&D Director, Synopsys

Kamal Desai, Principal Product Manager, Synopsys

B-102: Applications - 1 (Interfaces & Integrations Track)
Using Chiplets in Low-End Devices - Click for Proceedings
Jeff Gambino, staff, onsemi

Gareth Weale, Product Marketing Manager, onsemi
Chiplets for Automotive Applications: Current Status - Click for Proceedings
Andy Heinig, Leader Advanced Packaging Working Group, Fraunhofer IIS

Enabling Chiplet Reuse Through Standardization - Click for Proceedings
Mark Knight, Director of Product Management, Arm

C-102: High Bandwidth Memory (Panel Track)
D-102: Annual Update on Die-to-Die Interfaces (Annual Update Track)
E-102: Best Packaging Methods for Your Application (sponsored by Amkor) (Panel Track)
Panel Members:
Panelist: Mike Kelly, VP Advanced Packaging, Amkor

Panelist: Kenneth Larsen, Director Product Marketing, Synopsys

Panelist: Chintan Buch, Sr Member Technical Staff Packaging, AMD

Panelist: Craig Bishop, Senior Engineer, Deca Technologies

Panelist: Kunal Parekh, Process Integration Manager, Micron

A-103: STCO/AI (sponsored by Synopsys) (Design/Security Track)
Overview of the OCP Whitepaper on STCO
Raghu Shenkar, Independent Entrepreneur, Entrepreneur

Using Federated Simulation as a Framework for Chiplet-Based Design - Click for Proceedings
Kevin Cameron, Consultant, Cameron EDA

Extending Hardware/Software Co-Design to Chiplets
Arindam Mallik, Department Director, Compute System Architecture, imec

B-103: Interfaces - 2 (sponsored by Eliyan) (Interfaces & Integrations Track)
Reusable Family of Elements for Chiplet-Based Design
Sue Hung Fung, Principal Product Marketing Manager, Chiplets, Alphawave Semi

Sridhar Valluru, Principal Product Marketing Manager, Chiplets, Arm
New High-Speed Memory Interface for Demanding Applications
Paul Hylander, Chief Architect, Eliyan

Verifying Multi-Die Designs Using UCIe 2.0 Features - Click for Proceedings
Luis Li, Senior Software Engineer, Siemens

Prashant Dixit, Senior Software Engineer, Siemens

C-103: Best Way to Optimize Chiplets (Panel) (Panel Track)
Panel Members:
Panelist: Mick Posner, VP HPC Interfaces, Synopsys

Panelist: Vidyasagar Ganesan, Director, AMD

Panelist: Nandan Nayampally, CCO, Baya Systems

Panelist: Saptadeep Pal, Chief Architect, Etched

D-103: Annual Update on Chiplet Design (sponsored by Alchip Technologies) (Annual Update Track)
E-103: Package Development (sponsored by MRSI Mycronic) (Packaging Track)
Applying Co-Design/Co-Verification to Multi-Die Designs with Advanced Packaging - Click for Proceedings
Shawn Nikoukary, Sr Director Advanced Packaging, Synopsys

Best Practices for Testing 2.5D Chiplet Package Designs - Click for Proceedings
Vineet Pancholi, Sr. Director, Amkor

Extending Verification and Validation to Multi-Die Designs - Click for Proceedings
Levent Caglar, Executive Director - Product Management, Synopsys