Multi-Die Design from Architecture Exploration to Signoff - Click for Proceedings
Rita Horner, Sr Director Product Marketing, Synopsys

Chiplet Packaging Basics - Click for Proceedings
Roger St Amand, Chief Vice President, Chiplets/FCBGA, Amkor

Chiplet Integration Basics - Click for Proceedings
Naran Viswanathan, Signal Integrity Engineer, Intel

Chiplet Testing Basics - Click for Proceedings
Jeorge Hurtarte, Sr Director Product Marketing, Teradyne

Welcome/Introduction
Laura Mirkarimi, VP 3D Technologies, Adeia

Better Sort Processes Improve Advanced Packaging and Chiplet Manufacturing - Click for Proceedings
Patrick Pisano, Director Test Strategy, Intel Foundry

Chiplets and Advanced Packaging Provide Denser, Faster Chips
Adrienne Downey, Market Research Analyst, TechInsights

Implementing UCIe with Standard and Advanced Packaging
Daniel Lambalot, Sr. Principal Engineer, Alphawave Semi

Rapid & Unified Manufacturing Services for Next-Generation Devices and Packages
Rozalia Beica, Field CTO, packaging, Rapidus Design Solutions

Next-Gen Connectivity: Glass-Based Substrate Solutions for Ultra High Bandwidth
Sung Jin Kim, CTO, Absolics

Speaker: Jonathon Evans, Principal Architect, NVIDIA

Panelist: Randy White, , Keysight Technologies

Panelist: Sridhar Valluru, Principal Product Marketing Manager, Chiplets, Arm

Speaker: Sridhar Valluru, Principal Product Marketing Manager, Chiplets, Arm

Speaker: Pedro Merlo, Manager of Strategic Planning, Keysight Technologies

Speaker: Jerome Glisse, Software Engineer, Google

Speaker: Letizia Giuliano, VP Solutions Engineering, Alphawave Semi

Panelist: Jonathon Evans, Principal Architect, NVIDIA

Panelist: Letizia Giuliano, VP Solutions Engineering, Alphawave Semi

Speaker: Chang-Hyo Yu, Chief Architect, Rebellions

Panelist: Gerald Pasdast, Sr Principal Engineer, Intel

Speaker: Gerald Pasdast, Sr Principal Engineer, Intel

Welcome/Introduction to Die-to-Die Interfaces - Letizia Giuliano, VP Solutions Engineering, Alphawave Semi
UCIe Layered Approach to Die-to-Die Interface - Gerald Pasdast, Sr Principal Engineer, Intel
UCIe Offers Flexible Manageability and Security - Jerome Glisse, Software Engineer, Google
Die-to-Die Interoperability: Breakthroughs in AI with Chiplets - Sridhar Valluru, Principal Product Marketing Manager, Chiplets, Arm
Jonathon Evans, Principal Architect, NVIDIA
Developing a Die-to-Die Interface for a Scalable Chiplet Technology - Chang-Hyo Yu, Chief Architect, Rebellions
Using Golden Die in Interface Testing - Pedro Merlo, Manager of Strategic Planning, Keysight Technologies
Panel: Choosing the Best Interface for Your Application - Joshua Rubin, Sr Engineer, IBM Research
Letizia Giuliano, VP Solutions Engineering, Alphawave Semi
Gerald Pasdast, , Intel

Ultra-Low Latency
David Lariviere, Professor, University of Illinois

Reliability and Security
Ariel Hendel, , Intel

Chihjen Chang (CJ), SoC Chief Architect, Intel
Anjali S. Jain, , Awumba
Introduction to the Ethernet 2025 Workshop
Paul Borrill, Chief Product Officer, Daedaelus

Applying Digital Twin Technology to Chiplet Development
Andy Heinig, Leader Advanced Packaging Working Group, Fraunhofer IIS

Kevin Yee, Sr. Directory of Foundry Marketing, Samsung Semiconductor
Jonathan Smith, , Cadence
Modular Hardware-Assisted Approach to Multi-Die Verification - Click for Proceedings
Frank Schirrmeister, Executive Director, Strategic Programs, Systems Solutions, Synopsys

Distributed Large-Scale AI Systems Use Chiplets with Optical Interconnect
Denis Dutoit, Sr Project Leader, CEA-List

Simplifying the Use of Co-Packaged Optics with Chiplets
Sylvie Joly, Partnerships Manager 3D integration & packaging, CEA-List

Chiplet Architecture for Large Capacity CXL Memory Applications
Dongsop Lee, Director, SK hynix

Minsoon Hwang, Director, SK hynix

Panel: Key Issues in Working with Foundries - Click for Proceedings
Kevin Yee, Sr. Directory of Foundry Marketing, Samsung Semiconductor

Emmanuel Ollier, Head of Laboratory, CEA-Leti
Marc Hutner, , Siemens
Engaging Foundries to Deliver Chiplet-Based SoC's - Click for Proceedings
Marc Meunier, Director of Ecosystem Development, Arm

Building Your Chiplets with Foundry! - Click for Proceedings
Kevin Yee, Sr. Directory of Foundry Marketing, Samsung Semiconductor

Efficient Integration of Chiplets in a 3DIC R&D Foundry - Click for Proceedings
Emmanuel Ollier, Head of Laboratory, CEA-Leti

Achieving On-Time Delivery of Production-Ready Designs - Click for Proceedings
Marc Hutner, Director of Product Management for Tessent Yield Learning, Siemens

Unlocking Chiplets: Exploring Innovative Architectures and Remote Simulation Tec
Kevin Jennings, Design Engineering Architect, Cadence

Junie Um, Distinguished Engineer, Cadence
Unifying Chiplets: Enabling Die to Die Connectivity
Sue Hung Fung, Product Product Marketing Manager, Alphawave Semi

UCIe Enablement of AMD Versal Chiplet
Millind Mittal, Sr Fellow – Strategic Architecture Initiatives, AMD

Simulation Based Interoperability to Accelerate Adoption of Chiplet Standards - Click for Proceedings
Justin Bunnell, Technical Product Manager, Siemens

Optical Retimer Chiplets for the Next Wave of AI Infrastructure
LK Bhupathi, VP, Products & Strategy, Ayar Labs

Enabling Chiplet Reuse and Composable SoCs Through Chiplet Standardization
Mark Knight, Director of Product Management, Arm

Panel: Solving the Major Problems in Die-to-Die Interface Implementation Today
Umit Ogras, Associate Professor, University of Wisconsin

LK Bhupathi, VP, Products & Strategy, Ayar Labs
Millind Mittal, , AMD

The Open Chiplet Economy Marketplace Is Open - Click for Proceedings
Anu Ramamurthy, OCP Project Co-Lead, Open Compute Project

Business Analysis and Tradeoffs for Chiplet-Based System Design - Click for Proceedings
Raghu Shankar, , Chiplets Entrepreneur

Steve Helvie, VP Channel Development, Open Compute Project
Breaking Down Barriers to Using Chiplets (Panel) - Click for Proceedings
Cliff Grossner, Chief Innovation Officer, Open Compute Project

Standarized Metrics for Chiplet Interconnect (PHY) Comparison - Click for Proceedings
Shahab Ardalan, Co-Founder - Vice President Of Engineering, Enosemi

Imagine a World with an Abundance of Wires - Click for Proceedings
Jawad Nasrullah, CEO, Palo Alto Electron

How d-Matrix Is Leveraging ODSA’s BoWDie-to-DieLink to Transform Generative AI - Click for Proceedings
Keith Nellis, , d-Matrix

Modularity for High Performance Computing (HPC) and Artificial intelligence (AI) - Click for Proceedings
Patricia Gonzalez, Research Scientist, Lawrence Berkeley Laboratory

Business Analysis and Tradeoffs for Chiplet-Based System Design
Raghu Shankar, , Chiplets Entrepreneur

Steve Helvie, VP Channel Development, Open Compute Project
BoW PHY 2.1
Elad Alon, CEO, Blue Cheetah

Kevin Donnelly, VP Strategic Marketing, Eliyan
Kash Johal, , YorChip
Effective Management of Chiplet IP for Successful Designs - Click for Proceedings
Vishal Moondhra, VP Solutions, Perforce

Chiplet-based SiP Testing: Challenges and Solutions - Click for Proceedings
Aparna Tarde, Product Manager, Synopsys

Rajesh Pendurkar, Director Silicon Engineering, Capgemini
3D-IC Design Kits Help Produce Drop-in Chiplets - Click for Proceedings
David Ratchkov, CEO, Thrace Systems

James Wong, CTO, Palo Alto Electron

Panelist: Simon Rance, General Manager - Process and Data Management, Keysight Technologies

Panelist: Paul Borrill, Chief Product Officer, Daedaelus

Panelist: Frank Schirrmeister, Executive Director, Strategic Programs, Systems Solutions, Synopsys

Panelist: Sailesh Kumar, CEO, Baya Systems