Thursday, January 26th
A-201: Interfaces (Design/Packaging/Interfaces/Applications Track)
Creating a Sound Die-to-Die Interface for Today's Chiplet-Based Designs - Click for Proceedings
Letizia Giuliano, VP Solution Engineering, Alphawave SEMI

Performance and Reliability Monitoring of Die-to-Die Interfaces - Click for Proceedings
Nir Sever, Sr. Director, Business Development at proteanTecs, proteanTecs

UCIe: An Open Standard Interface for Chiplet-Based Multi-Die Systems - Click for Proceedings
Manuel Mota, Sr Staff Product Marketing Manager, Synopsys

Simplifying Chiplet Interconnect Development with Interface IP
Manmeet Walia, Director Product Marketing, Synopsys

B-201: Partitioning (Disaggregation) (Partitioning/Integration/Test Track)
Guidelines for Designing Chiplet-Based Processors
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Chiplet Partitioning Can Balance Among Performance, Flexibility, and Scalability - Click for Proceedings
Denis Dutoit, Sr Project Coordinator, CEA-List

C-201: Best Packaging for Chiplets Today Panel (sponsored by ASE) (Panel Track)
Panel Members:
Panelist: Daniel Lambalot, Sr Principal Engineer, Alphawave Semi

Panelist: Laura Mirkarimi, VP 3D Technologies, Adeia

Panelist: Syrus Ziai, VP Engineering, Eliyan

Panelist: Dick Otte, CEO, Promex Industries

Panelist: Mike Kelly, VP Advanced Packaging Technology Integration, Amkor Technology

D-201: Annual Update on Test of Multi-Die Designs (Annual Update Track)
Annual Update on Test of Multi-Die Designs
Mike Ricchetti, SoC/DFT Architect, Synopsys

Yervant Zorian, Chief Architect/Fellow, Synopsys

A-202: Packaging - 2 (Design/Packaging/Interfaces/Applications Track)
Warpage Simulation for Assessing Chip-Package Interaction in 3D Stacks - Click for Proceedings
Junho Choy, Engineer, Siemens EDA

Successful Implementation of Chiplet-Based Heterogeneous Advanced Packages - Click for Proceedings
Keith Felton, Product Marketing Manager, Siemens EDA

B-202: How to Make Chiplets a Viable Market (Panel) (Panel Track)
Panel Members:
Panelist: Durgesh Srivastava, Sr Director, NVIDIA

Panelist: Clint Walker, VP Marketing, Alphawave SEMI

Panelist: Mark Kuemerle, VP/CTO ASIC Business Unit, Marvell

Panelist: Travis Lanier, VP Marketing, Ventana Micro Systems

Panelist: Kevin Yee, Director IP Marketing, Samsung Semiconductor

C-202: Highlights from University Research on Chiplets (Academic Track)
Designing a 2000 Chiplet Waferscale Processor - Click for Proceedings
Puneet Gupta, Professor, UCLA

A New Heterogeneous Chiplet-Based Architecture for AI Computing - Click for Proceedings
Yu Cao, Professor, Arizona State University

AI Chiplet Set for Inference and Training with Supply Chain Security - Click for Proceedings
Paul Franzon, Professor, North Carolina State University

Chiplet-Based Image Processor for Wide-Area Surveillance
Andreas Andreou, Professor, Johns Hopkins University

A-203: Design - 2 (Design/Packaging/Interfaces/Applications Track)
Using AI to Speed up Power Analysis for Chiplet Based Designs
Kendall Hiles, Sr Product Specialist High Density Packaging, Siemens EDA

Innovative Method for Automated Chiplet Assembly and Physical Verification
John Ferguson, Director Product Management, Siemens EDA

B-203: Chiplets in 2028 and How We Got There (Panel) (Panel Track)
Panel Members:
Panelist: Tom Hackenberg, Principal Analyst, Yole Intelligence

Panelist: John Shalf, Department Head, Lawrence Berkeley National Laboratory

Panelist: Jawad Nasrullah, CEO, Palo Alto Electron

Panelist: Omar Hassen, SVP Business Development, Ventana Micro Systems

Panelist: Bapi Vinnakota, ODSA Project Lead, Open Compute Project

Panelist: Millind Mittal, VP Data Center Technologies, AMD