Wednesday, January 25th
Chiplets: Where We Are Today (Plenary Track)
Chiplets Market Update - Click for Proceedings
Tom Hackenberg, Principal Analyst, Yole Intelligence

State of Chiplets Today - Click for Proceedings
Jawad Nasrullah, CEO, Palo Alto Electron

A-101: Packaging - 1 (Design/Packaging/Interfaces/Applications Track)
Improving Electromagnetic Simulation for Chiplet-Based IC Designs - Click for Proceedings
Feng Ling, CEO & Founder, Xpeedic

Handling Thermo-Mechanical Stress in Chiplets - Click for Proceedings
John Wilson, Business Development Mgr, Siemens EDA

Improved Process for Thin Glass Interposers
David Levy, Dir. R&D, Mosaic Mircosystems

B-101: Integration - 1 (sponsored by EMD Electronics) (Partitioning/Integration/Test Track)
Using High-Performance FPGA Chiplets in Heterogenous Systems - Click for Proceedings
Nick Ilyadis, Sr. Director of Product Planning, Achronix

Optimizing Chiplets Using Heterogeneous Integration and Co-Optimization - Click for Proceedings
Per Viklund, Director IC Packaging, Siemens EDA

Developing an FPGA Chiplet
Kash Johal, VP of Sales, eTopus

Mao Wang, Director Product Marketing, QuickLogic

C-101: Overcoming Chiplet Design Challenges - How Industry Can Help (Panel) (Panel Track)
Panel Members:
Panelist: Patrick Soheili, Co-Founder, Eliyan

Panelist: Rishi Chugh, VP Product Marketing, Cadence

Panelist: Luis Rodriguez, Senior Solutions Architect, Avery Design Systems

Panelist: Nir Sever, Sr. Director, Business Development at proteanTecs, proteanTecs

Panelist: Mark Kuemerle, VP/CTO ASIC Business Unit, Marvell

C-101 Panel Presentation - Jean Bozman, President/Chief Analyst, Cloud Architects - Click for Proceedings

D-101: Annual Update on Packaging (Annual Update Track)
Annual Update on Packaging - Click for Proceedings
Andy Heinig, Group Leader, Fraunhofer IIS

A-102: Applications (Design/Packaging/Interfaces/Applications Track)
Dynamically Reconfigurable Chiplet Substructures Advance Distributed Computing
Paul Borrill, CEO, Daedaelus

Using Chiplets to Develop Advanced Driver Assistance Systems (ADAS) for Vehicles - Click for Proceedings
Andy Heinig, Group Leader, Fraunhofer IIS

Chiplet-Based Switch SoC for CXL Resource Pooling
Shreyas Shah, CTO,

B-102: Test (Partitioning/Integration/Test Track)
DFT Architecture for Chiplet-based Systems in Package - Click for Proceedings
Rajesh Pendurkar, Director, Capgemini

Micro-Textured Film Aids in Universal Handling of 3D Devices
Raj Varma, CTO, Delphon/Gel-Pak

C-102: Best Way to Optimize Chiplets (Panel) (Panel Track)
Panel Members:
Panelist: Kenneth Larsen, Director Product Management, Synopsys

Panelist: Jonathon Evans, Principal Architect, NVIDIA

Panelist: Elad Alon, CEO & Co-founder, Blue Cheetah Analog Design

Panelist: Ramin Farjad, CEO, Eliyan

Panelist: Ken Chang, Corporate VP Design IP Engineering, Cadence

D-102: Annual Update on Chiplet Design: Multi-Die System in the post Moore Era (Annual Update Track)
Annual Update on Chiplet Design: Multi-Die System Design in the SysMoore Era
Shekhar Kapoor, Sr. Director of Product Marketing, Synopsys

A-103: Design - 1 (Design/Packaging/Interfaces/Applications Track)
Bringing Persistent Memory to Chiplets - Click for Proceedings
Bill Gervasi, Principal Systems Architect, Nantero

Energy-Centric AI Acceleration with Chiplet Based Design - Click for Proceedings
Robert Beachler, VP Product, Untether AI

Managing IP During Chiplet Design and Integration - Click for Proceedings
Michael Munsey, Sr Director Semiconductor/IP Solutions, Siemens EDA

B-103: Integration - 2 (Partitioning/Integration/Test Track)
Developing and Managing System Netlists for Chiplet Integration - Click for Proceedings
Mike Walsh, Technical Director – IC Packaging Solutions, Siemens

Simple, Low-Cost Method for Connecting Off-the-Shelf Chiplets - Click for Proceedings
Ramin Farjadrad, CEO, Eliyan

Using Predictive SI Analysis to Ensure Successful Chiplet Integration - Click for Proceedings
Subramanian (Lal) Lalgudi, Analysis/Verification Product Specialist, Siemens EDA

C-103: Next Great Breakthrough in Chiplets (Panel) (Panel Track)
Panel Members:
Panelist: Erez Shaizaf, CTO, Alchip

Panelist: Robert Patti, President, nHanced Semiconductors

Panelist: Craig Bishop, CTO, Deca

Panelist: Mike Li, VP Engineering/New Products, Corigine

D-103: Annual Update on Interfaces (Annual Update Track)
Annual Update on Interfaces - Click for Proceedings
Mick Posner, Product Line Sr Group Director, Synopsys