Integrating Chiplets into Large SiP Systems - Click for Proceedings
David Ratchkov, CTO, Anemoi Software

Moving IC Design from SoC to Chiplet-based SiP - Click for Proceedings
Gordon Allan, Product Manager, Siemens EDA

Chiplet Testing Basics
Yervant Zorian, Chief Architect/Fellow, Synopsys

Chiplets: A New Approach to Better Chips at Smaller Dimensions
Matthew Ouellette, Director Silicon Product Planning, AMD

Practitioner's View of Chiplet Packaging
Larry Zu, President, Sarcina Technology

Issues in Advanced Packaging for Chiplets
Lihong Cao, Director Engineering, ASE Group

Introduction to Advanced Packaging for Chiplets
Lihong Cao, Director Engineering, ASE Group

Adaptive Patterning in Advanced Packaging Methods - Click for Proceedings
Craig Bishop, CTO, Deca

Chiplet Integration Based on Design for Manufacturability and Cost Factors
Sam Salama, CEO, Hyperion

An Open Interconnect Standard Between Chiplets Within a Package
Gerald Pasdast, Form Factor and Compliance Working Group Chair, UCIe™ Consortium

Introduction to Die-to-Die Interfaces
Anu Ramamurthy, Staff Engineer, Microchip

Chiplet Integration on Advanced Packaging and System Realization Opportunities
Atom Watanabe, Research Staff Member, IBM

Choosing the Best Interface for Your Application Panel - Click for Proceedings
Gerald Pasdast, Form Factor and Compliance Working Group Chair, UCIe™ Consortium

Letizia Giuliano, VP Solution Engineering, Alphawave SEMI
Paul Borrill, , Daedaelus

Heterogeneous Design Methods - Click for Proceedings
Tony Mastroianni Intro, Advanced Packaging Solutions Director, Siemens Digital Industry Software

Designing for Power, Performance, and Area (PPA) for Multi-Die and 3D ICs
Kenneth Larsen, Director Product Marketing, Synopsys

Designing the ASIC You Want - with Chiplets
Carlos Macian Ruiz, ASIC System Architect, Marvell

Processor Cores for Chiplet Applications
David Kruckemyer, Principal Engineer, Ventana Micro Systems

Simplifying Chiplet-Based Development with Hardware Emulation Tools - Click for Proceedings
Mike Li, VP of Engineering & New Products, Corigine

Defining Appropriate Chiplet Models - Click for Proceedings
Tony Mastroianni, Advanced Packaging Solutions Director, Siemens Digital Industry Software

Some Like It Hot: The Complete Guide to Thermals for Chiplets - Click for Proceedings
David Ratchkov, CTO, Anemoi Software

Thermal Characterization and Modeling of Heterogeneous Packages - Click for Proceedings
Andras Vass Varnai, Portfolio Development Executive, Siemens EDA

Large System Design of a 6-Chiplet Based Architecture - Click for Proceedings
Pascal Vivet, Scientific Director, CEA-List

Managing Heat and Power in Today's Chiplet-Based Designs - Click for Proceedings
Robert Patti, President, nHanced Semiconductors

Hybrid Bonding Technology for Chiplet Integration
Laura Mirkarimi, VP 3D Technologies, Adeia

Test Impacts of Multi-Die Packages
Vineet Pancholi, Sr Director Test Technology, Amkor

Applying Design for Test (DFT) to 3D IC Assemblies
Vidya Neerkundar, Product Marketing Manager, Siemens

Incorporating Design-for-Test into the Development of Chiplet-Based Systems - Click for Proceedings
Adam Cron, Distinguished Architect, Synopsys

Achieving More Efficient Test for Chiplet-Based Designs
Andrei Berar, Sr Director Test Business Development, Amkor Technologies

Part 4 – Arming the Vendors and Builders of the Chiplet Economy
James Wong, CTO, Palo Alto Electron

Elad Alon, CEO & Co-founder, Blue Cheetah Analog Design
Kash Johal, , eTopus
Die-to-die (D2D) Interface for Multi-Chiplet AI Systems
Sid Sheth, CEO, d-Matrix

Part 2 – Why the Market Demands Chiplets
Dharmesh Jani, Open Source Ecosystem Leader, Meta

Amber Huffman, Lead Technologist, Google
John Shalf, , Lawrence Berkeley National Laboratory
Part 3 – Developing Chiplets and Systems-in-Package (SiPs)
Sid Sheth, CEO, d-Matrix

Jayaprakash (JP) Balachandran, Signal Integrity Engineer, Cisco Systems
Arvind Kumar, , IBM
Chiplet Innovation Ecosystem - Click for Proceedings
Amber Huffman, Lead Technologist, Google

Chiplets in High-Performance Computing (HPC) - Click for Proceedings
John Shalf, Department Head, Lawrence Berkeley National Laboratory

PHY Interoperability Testing
Jayaprakash Balachandran, Signal Integrity Engineer, Cisco Systems

One Click Chiplet Interconnect - Click for Proceedings
Elad Alon, CEO & Co-founder, Blue Cheetah Analog Design

Eliminating the Risk of Malicious Counterfeit Chiplet Components - Click for Proceedings
Scott Best, Technical Director, Rambus

Drop in FPGA Chiplet - Click for Proceedings
Kash Johal, VP of Sales, eTopus

Part 1 - Introduction
Bapi Vinnakota, ODSA Project Lead, Open Compute Project

Panel: What Does an Open Chiplet Economy Require?
Tom Hackenberg, Principal Analyst, Yole Intelligence

John Shalf, Department Head, Lawrence Berkeley National Laboratory
Alvin Loke, , NXP Semiconductors
Chiplets Meet the Needs of Cloud Services Using AI/ML
Dharmesh Jani, Open Source Ecosystem Leader, Meta

The Emerging Chiplet Economy
Bapi Vinnakota, System Architect, Broadcom

Using a Markup Language in Chiplet-Based Design - Click for Proceedings
James Wong, CTO, Palo Alto Electron

Panelist: Brett Wilkerson, Product Development Engineer, AMD

Panelist: Marcus Pan, Program Manager, Semiconductor Research Corporation (SRC)

Panelist: John Ferguson, Director Product Management, Siemens EDA

Panelist: Paul Franzon, Professor, North Carolina State University

Panelist: Bob Patti, CEO, nHanced Semiconductors