| Thursday, June 15th |
Thursday, June 15th
09:00-10:00 AM | | A-201: Network Acceleration 2 - High-Performance Systems (Networking Track) | | Moderator: Donglai Dai, Chief Engineer, X-ScaleSolutions | Paper Presenters:
| Accelerating Open Virtual Switch (OVS) Using P4 and IPDK
Deb Chatterjee, Network Acceleration Team Lead, IntelFPGA-Based SmartNICs Process Packets at 400 Gbps+
Lukas Kekely, CTO, BrnoLogic | Session Description:
| High-performance applications typically require FPGA-based devices to provide enough bandwidth. It takes high-powered SmartNICs to handle virtual switches and Ethernet networks at 100 Gbps and above. Both the P4 network programming language and the IPDK development kit are useful in producing such applications.
| | About the Organizer/Moderator: | Donglai Dai is Chief Engineer at X-ScaleSolutions, where he leads the company's R&D team. His current work focuses on developing and enhancing communication libraries, checkpointing and restart libraries, performance analysis tools for distributed and parallel HPC and deep learning applications on HPC systems and clouds. He is the principal investigator for several DOE SBIR grants and a member of the checkpoint restart standard steering committee. Before joining X-Scale Solutions, he worked at Intel, Cray, and SGI. He holds over 10 US patents and has published over 40 technical papers, presentations, or book chapters. He earned a PhD in computer science from Ohio State University.
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Thursday, June 15th
09:00-10:00 AM | | B-201: Software 2 - Drivers and Managers (Software Track) | | Moderator: Pawel Duleba, Sr Software Engineer, CodiLime | Paper Presenters:
| Writing Universal DPDK Drivers for SmartNICs
Jan Zieleznicki, Sr Software Engineer, CodiLimeDeveloping Secure IPU/DPU Device Management
Naru Sundar, Principal Engineer, Intel | Session Description:
| The programmability of SmartNICs is obviously a huge advantage, allowing them to take on a variety of tasks and be updated as needed. However, it does complicate the software. Drivers become more complex, as does device management. Software is flexible, but developing it is expensive. And there always seems to be a need for more utilities unrelated to the actual applications.
| | About the Organizer/Moderator: | Pawel Duleba is a Sr Software Engineer at Codilime, where he works as a full stack application developer. He currently focuses on low-level programming and optimization for SmartNIC applications. He has over 10 years experience working on advanced Web and full-stack applications, networking, and SDN. He earned an MS in information technology from the University of Gdansk.
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Thursday, June 15th
09:00-10:00 AM | | C-201: Best Way to Accelerate Networks Today Panel (sponsored by Chelsio) (Panels Track) | | Moderator: John Kim, Director Storage Marketing, NVIDIA | Panel Members:
| Panelist: Jon Sreekanth, Architect, AchronixPanelist: Anu Murthy, VP Product, FADUPanelist: Venkat Pullela, Chief Of Technology, Networking, Keysight TechnologiesPanelist: Rochan Sankar, CEO, EnfabricaPanelist: Bob Dugan, Program Manager, Chelsio CommunicationsPanelist: Trevor Caulder, Principal Developer/Advocate, NVIDIA | Session Description:
| Network acceleration is a major application for SmartNICs. The major clouds all use them to handle their huge and ever-changing application workloads. Telcos use them to implement virtualization (NFV) and to provide easy upgrades and higher modular modularity and scalability. Enterprise networks use them to avoid overburdening CPUs and to simplify the addition of new or updated services.
| | About the Organizer/Moderator: | John Kim is director of storage and DPU marketing in NVIDIA’s networking division. He<br>helps customers and vendors benefit from high-performance network connections, SmartNIC offloads, and DPU acceleration, especially for storage, big data, AI and cybersecurity. A frequent blogger, conference speaker, and webcast presenter, John was chair of SNIA’s Networking Storage Forum. Before joining NVIDIA, he worked in solution marketing, product management, and alliances at NetApp and EMC. He earned a BA in economics from Harvard.
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Thursday, June 15th
02:00-3:20 PM | | A-202: Application Acceleration 1 - Special Workloads (Application Acceleration Track) | | Moderator: Addison Snell, CEO, Intersect360 Research | Paper Presenters:
| SmartNICs and DPUs Accelerate HPC Solutions
Scot Schultz, Sr Director - HPC & Technical Computing, NVIDIAAccelerating HPC and Deep Learning (DL) Applications with SmartNICs - Click for Proceedings:
Donglai Dai, Chief Engineer, X-ScaleSolutionsIdentifying Workloads Well-Suited to Acceleration by IPUs
Yadong Li, SW Architect, Intel | Session Description:
| Although networking is the obvious major application of SmartNICs, they can also handle a wide variety of other use cases, such as HPC and deep learning (DL). Methods are available to identify applications well-suited to acceleration with IPUs/DPUs/SmartNICs.
| | About the Organizer/Moderator: | Addison Snell is the CEO of Intersect360 Research and a veteran of the high performance computing (HPC) industry. He has established Intersect360 Research as a premier source of market information, analysis, and consulting. He was named one of 2010's "People to Watch" by HPCwire. He is a regular participant at both Supercomputing and the ISC High-Performance conferences as a speaker, panelist, and chairperson. Before co-founding Intersect360, Addison was an HPC industry analyst for IDC, where he was well-known among industry stakeholders. Before joining IDC, he was a marketing leader and spokesperson for SGI's supercomputing products and strategy. Addison holds a master's degree from the Kellogg School of Management at Northwestern University and a bachelor's degree from the University of Pennsylvania.
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Thursday, June 15th
02:00-3:20 PM | | B-202: Best Architecture for SmartNICs Today Panel (Panels Track) | | Moderator: Manoj Roge, , Consultant | Panel Members:
| Panelist: Eyal Tokman, DPU Architect, NVIDIAPanelist: Raymond Nijssen, VP/Chief Technologist, AchronixPanelist: DK Panda, Professor/Distinguished Scholar, Ohio State UniversityPanelist: Vikram Singh, Sr Product Line Manager, Juniper NetworksPanelist: Rich Cahill, Data Center Acceleration Engineer, Intel | Session Description:
| Current SmartNIC architectures offer many tradeoffs. Ones based on ASICs or FPGAs are generally faster and easier to implement. Those based on standard processors are more flexible and easier to update. Coprocessors such as GPUs or DPUs increase performance but are expensive and difficult to program. Most observers expect the software-based devices to dominate the market because of their flexibility, but performance issues could leave a substantial market for hardware-based SmartNICs. The cost and time requirements for developing typical applications for processor-based SmartNICs is as yet unknown, but could have a big effect.
| | About the Organizer/Moderator: | Manoj Roge is a product marketing and management professional specializing in AI, data center, and communications technologies. He previously led solutions planning<br>and marketing for CPU and DPU (Data Processing Unit) products at Marvell. He has also worked for Synopsys, Achronix, and Xilinx. His current interests are in CPU architecture, network processing, security, ASICs, and SmartNICs. He has presented at many conferences, including Design Automation Conference (DAC), Flash Memory Summit, Open Compute Project (OCP) Global Summit, and the International SoC Conference. He has also written articles and whitepapers and holds several patents. He earned an MSEE in VLSI Design from University of Texas at Arlington.
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Thursday, June 15th
02:00-3:20 PM | | C-202: Academic Research Review (Academic Track) | | Moderator: Ming Liu, Assistant Professor/Researcher, University Wisconsin - Madison/VMware | Paper Presenters:
| New Packet Queuing Method Allows for Protocol Updates and Switch Enhancements
Costin Raiciu, Professor, University Politehnica - BucharestNetwork Stack that Allocates Resources Independently in Each Layer
Qizhe Cai, PhD Student, CornellNew TCP Stack Offloads Content Delivery I/O to a SmartNIC - Click for Proceedings:
Taehyun Kim, Graduate Student, KAISTFpgaNIC: A Versatile FPGA-based 100Gb SmartNIC for GPUs - Click for Proceedings:
Jie Zhang, Graduate Student, Zhejiang University | Session Description:
| Academic research in SmartNICs has progressed rapidly in the past few years. There are many interesting contributions in the following general areas: - Architectures - Transport - Application Services - Programming Language Support Industry will surely find many projects to be of immediate interest to them for both ideas and personnel. This year’s subjects include improved network stacks, a 100 Gbps SmartNIC that handles GPUs, content delivery, and improved packet queuing. Several projects indicate that the resulting software could easily be loaded into a SmartNIC to avoid burdening a central CPU.
| | About the Organizer/Moderator: | Ming Liu is an Assistant Professor in the Computer Sciences Department at the University of Wisconsin – Madison. His research covers networking and systems, with a focus on network-based hardware acceleration. His projects include NVMe-oF targets for SmartNIC JBOFs, using SmartNICs to accelerate distributed transaction processing and offload actor-based distributed applications, and developing automated offloading insight for SmartNICs and using a data-flow based programing system for developing SmartNIC applications. He earned his PhD at the University of Washington and was a postdoctoral researcher at VMware. He has 14 published conference papers, including ones at the USENIX Symposium on Operating Systems Design and Implementation, (OSDI), Architecture Support for Programming Languages and Operating Systems (ASPLOS), and ACM Symposium on Operating Systems Principles (SOSP).
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Thursday, June 15th
03:30-5:00 PM | | A-203: Application Acceleration 2 - AI Applications (Application Acceleration Track) | | Paper Presenters:
| Using SmartNICs to Achieve the Promise of ChatGPT
Itay Ozery, Director Product Management, NVIDIA | Session Description:
| AI is clearly a major emerging application for SmartNICs. AI applications always need more computing power, and SmartNICs are an obvious way to provide it. An emerging class of AI applications are the so-called formative systems, such as the incredibly popular ChatGPT. Their basic engine requires tremendous amounts of processing andadd-ins can increase the requirements even further.
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Thursday, June 15th
03:30-5:00 PM | | B-203: SmartNICs in 2028 and How We Got There Panel (sponsored by X-Scale) (Panels Track) | | Moderator: Bill Wong, Editor, Endeavor Business Media | Panel Members:
| Panelist: Baron Fung, Research Director, Dell'Oro GroupPanelist: Ahmet Houssein, CEO, SiPandaPanelist: Scott Schweitzer, Director SmartNIC Product Planning, AchronixPanelist: DK Panda, Professor/Distinguished Scholar, Ohio State University | Session Description:
| The five-year horizon for SmartNICs is very promising. They will make up an ever increasing part of the NIC market, as their cost is more than balanced by the tremendous capabilities they bring to networked systems. More canned software will be available for them, as well as development platforms, operating systems, utilities, and other tools. Standardization will be a major issue, as most large customers will want multiple sources as well as large ecosystems and wide support for both development and test. Other issues include achieving higher throughput and lower latency, isolating executing applications from one another, security, and operating system support.
| | About the Organizer/Moderator: | Bill Wong is Editor of Electronic Design Magazine, as well as Senior Content Director of its parent organization, Endeavor Business Media. One of the best-known editors in the technical press, he is noted for his interviews, analysis, and project articles. He focuses on embedded, software, and systems applications in the magazine. He has solid technical credentials, having earned a BSEE at Georgia Tech and an MSCS at Rutgers. He still works on hardware and software projects, including C, C++, and PHP programming and hardware ranging from robotics to AI systems.
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