Thursday, June 15th
Thursday, June 15th
09:00-10:00 AM
A-201: Network Acceleration 2 - High-Performance Systems (Networking Track)
Paper Presenters:
Accelerating Open Virtual Switch (OVS) Using P4 and IPDK
Deb Chatterjee, Network Acceleration Team Lead, Intel

FPGA-Based SmartNICs Process Packets at 400 Gbps+
Lukas Kekely, CTO, BrnoLogic

Session Description:
High-performance applications typically require FPGA-based devices to provide enough bandwidth. It takes high-powered SmartNICs to handle virtual switches and Ethernet networks at 100 Gbps and above. Both the P4 network programming language and the IPDK development kit are useful in producing such applications.
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Thursday, June 15th
09:00-10:00 AM
B-201: Software 2 – Drivers and Managers (Software Track)
Paper Presenters:
Writing Universal DPDK Drivers for SmartNICs
Jan Zieleźnicki, Sr Software Engineer, CodiLime

Developing Secure IPU/DPU Device Management
Naru Sundar, Principal Engineer, Intel

Session Description:
The programmability of SmartNICs is obviously a huge advantage, allowing them to take on a variety of tasks and be updated as needed. However, it does complicate the software. Drivers become more complex, as does device management. Software is flexible, but developing it is expensive. And there always seems to be a need for more utilities unrelated to the actual applications.
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Thursday, June 15th
09:00-10:00 AM
C-201: Best Way to Accelerate Networks Today Panel (sponsored by Chelsio) (Panels Track)
Panel Members:
Session Description:
Network acceleration is a major application for SmartNICs. The major clouds all use them to handle their huge and ever-changing application workloads. Telcos use them to implement virtualization (NFV) and to provide easy upgrades and higher modular modularity and scalability. Enterprise networks use them to avoid overburdening CPUs and to simplify the addition of new or updated services.
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Thursday, June 15th
02:00-3:20 PM
A-202: Application Acceleration 1 - Special Workloads (Application Acceleration Track)
Paper Presenters:
SmartNICs and DPUs Accelerate HPC Solutions
Scot Schultz, Sr. Director, HPC and Technical Computing, NVIDIA

Accelerating HPC and Deep Learning (DL) Applications with SmartNICs
Donglai Dai, Chief Engineer, X-ScaleSolutions

Identifying Workloads Well-Suited to Acceleration by IPUs
Yadong Li, SW Architect, Intel

Session Description:
Although networking is the obvious major application of SmartNICs, they can also handle a wide variety of other use cases, such as HPC and deep learning (DL). Methods are available to identify applications well-suited to acceleration with IPUs/DPUs/SmartNICs.
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Thursday, June 15th
02:00-3:20 PM
B-202: Best Architecture for SmartNICs Today Panel (Panels Track)
Panel Members:
Session Description:
Current SmartNIC architectures offer many tradeoffs. Ones based on ASICs or FPGAs are generally faster and easier to implement. Those based on standard processors are more flexible and easier to update. Coprocessors such as GPUs or DPUs increase performance but are expensive and difficult to program. Most observers expect the software-based devices to dominate the market because of their flexibility, but performance issues could leave a substantial market for hardware-based SmartNICs. The cost and time requirements for developing typical applications for processor-based SmartNICs is as yet unknown, but could have a big effect.
About the Organizer/Moderator:
Thursday, June 15th
02:00-3:20 PM
C-202: Academic Research Review (Academic Track)
Paper Presenters:
New Packet Queuing Method Allows for Protocol Updates and Switch Enhancements
Costin Raiciu, Professor, University Politehnica of Bucharest

Network Stack that Allocates Resources Independently in Each Layer
Qizhe Cai, PHD Student, Cornell

New TCP Stack Offloads Content Delivery I/O to a SmartNIC
Taehyun Kim, Graduate Student, KAIST

FpgaNIC: A Versatile FPGA-based 100Gb SmartNIC for GPUs
Jie Zhang, Gradudate Student, Zhejiang University

Session Description:

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Thursday, June 15th
03:30-5:00 PM
A-203: Application Acceleration 2 - AI Applications (Application Acceleration Track)
Paper Presenters:
Using SmartNICs to Achieve the Promise of ChatGPT
Itay Ozery, Director Product Management, NVIDIA

Session Description:
AI is clearly a major emerging application for SmartNICs. AI applications always need more computing power, and SmartNICs are an obvious way to provide it. An emerging class of AI applications are the so-called formative systems, such as the incredibly popular ChatGPT. Their basic engine requires tremendous amounts of processing andadd-ins can increase the requirements even further.
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Thursday, June 15th
03:30-5:00 PM
B-203: SmartNICs in 2028 and How We Got There Panel (sponsored by X-Scale) (Panels Track)
Panel Members:
Session Description:
The five-year horizon for SmartNICs is very promising. They will make up an ever increasing part of the NIC market, as their cost is more than balanced by the tremendous capabilities they bring to networked systems. More canned software will be available for them, as well as development platforms, operating systems, utilities, and other tools. Standardization will be a major issue, as most large customers will want multiple sources as well as large ecosystems and wide support for both development and test. Other issues include achieving higher throughput and lower latency, isolating executing applications from one another, security, and operating system support.
About the Organizer/Moderator: