Wednesday, June 14th
Wednesday, June 14th
09:00-10:00 AM
SmartNICs: Where We Are Today (sponsored by Synogate) (Plenary Track)
Moderator: Chuck Sobey, General Chair, SmartNICs Summit

Paper Presenters:
SmartNICs Market Update
Baron Fung, Research Director, Dell'Oro Group

State of SmartNICs Today
Scott Schweitzer, Director - SmartNIC Product Planning, Achronix

Session Description:
SmartNICs keep advancing with faster processors, more on-board accelerators and memory, and better support and management tools. The hyperscalers are leading the way with their demands for 100/200G networking, AI accelerators, and more switching, security, and virtualization features. They also want programming to be handled through already existing channels. Standardized approaches such as SONiC-DASH (using the widely deployed SONiC network operating system) and OPI (Open Programmable Infrastructure, an API that all vendors could use as a common interface) are drawing some interest. Many new use cases, including AI, security, content management, storage, and financial, have been reported, but protocol offload remains the most common application. Markets continue to expand, although most hyperscalers are still producing their own devices rather than using off-the-shelf products. Current predictions are for a total market of $2 billion in 2027, about equally split between hyperscalers and other customers. 100/200G is now the standard network speed, with the 40G/50G market dropping and 400G and 800G starting to emerge. Terabit Ethernet is not far off!
About the Organizer/Moderator:
Chuck Sobey is General Chair of SmartNICs Summit. He leads a team of industry veterans to organize the Summit, identifying key trends, topics, and speakers. Chuck is a respected memory and storage technology strategist, researcher, and lecturer. As Chief Scientist of ChannelScience, he guides clients in evaluating emerging memory and storage technologies and maximizing their reliability and performance. He uses probability analysis to match a technology's projected capabilities to an application's requirements. His team has won SBIR awards from the US Department of Energy to advance the field of magnetic tape recording, on which practically all of the hyperscale and cloud services rely. Chuck is also the Conference Chair of Flash Memory Summit, which he helped lead to become the number one independent storage event. He earned an MS ECE from the University of California, Santa Barbara and a BS ECE from Carnegie Mellon University. He holds 7 US patents.

Wednesday, June 14th
02:00-3:00 PM
A-101: Networking Applications 1 – Communications Issues (Networking Track)
Moderator: Ahmet Houssein, CEO, SiPanda

Moderator: Kimball Brown, Analyst, Analyst

Paper Presenters:
Using SONiC-DASH to Create Ultra-High-Speed Cloud Switches
Reshma Sudarshan, Director of Applications Engineering, Intel

Generating Packets with SmartNICs and the P4 Language
Marcin Parafiniuk, Senior Software Engineer, CodiLime

Session Description:
Networking is clearly the major application for SmartNICs and DPUs. They are used for many purposes, including packet generation and cloud network accelerators. One issue in all the applications is the difficulty of development. Available tools include the P4 network programming language, primarily intended for developing switches, and the SONiC-DASH extensions, primarily intended for SmartNIC/DPU deployment, provisioning, orchestration, and management.
About the Organizer/Moderator:
Kimball Brown is a Senior Alliances Advisor for the security software firm BlackRidge Technology. He was previously a Global Technical Strategist at VMware, where he engaged Cisco in co-development projects. He has also been a VP/Sr Datacom Analyst with LightCounting, a specialist group focused on high-speed interfaces and communications devices. He has experience with Broadcom and Dataquest as well. He earned an MBA from UC Berkeley and a BSEE from Duke University.

Kimball Brown is a Senior Alliances Advisor for the security software firm BlackRidge Technology. He was previously a Global Technical Strategist at VMware, where he engaged Cisco in co-development projects. He has also been a VP/Sr Datacom Analyst with LightCounting, a specialist group focused on high-speed interfaces and communications devices. He has experience with Broadcom and Dataquest as well. He earned an MBA from UC Berkeley and a BSEE from Duke University.

Wednesday, June 14th
02:00-3:00 PM
B-101: Data Center Applications (Data Centers Track)
Paper Presenters:
Offload More Functions to DPUs Using On-Board Low-Power Cores
Matthew Dirba, Staff Design Engineer, Arm

SmartNICs/DPUs Save Millions in Data Center Power Costs
John Kim, Director Storage Marketing, NVIDIA

Session Description:
SmartNICs can be useful in many data center applications. The most common use case is handling protocol overhead. However, they can also serve other purposes, such as: Encryption/decryption Storage services such as deduplication and mirroring Database or financial functions Security algorithms AI/ML processing Overhead functions such as software-defined storage and virtualization They are particularly well-suited to large clouds, which want to offload overhead activities so they can dedicate processors to chargeable tasks. And the typically high-powered devices can even reduce overall memory usage by making it unnecessary for data centers to buy additional servers, storage units, and switches just to get more processing power.
About the Organizer/Moderator:
Wednesday, June 14th
02:00-3:00 PM
C-101: Best Way to Program SmartNICs Today Panel (Panels Track)
Moderator: John Lockwood, CEO, Algo-Logic

Panel Members:
Panelist: Itay Ozery, Director Product Management, NVIDIA

Panelist: Vipin Jain, Sr Fellow Engineer, AMD

Panelist: Krzysztof Wrobel, Director Engineering, CodiLime

Session Description:
Software development is a major issue for SmartNICs, since it often takes a long time and is very expensive. Furthermore, the number of units is seldom large enough to allow amortization to have much effect. Also many standard operating systems and development environments are available only for X86 processors, not the ARM or RISC-V cores commonly used in SmartNICs. The addition of other computing elements such as GPUs, DPUs, and AI chips further complicates the process. Developers can counter such problems in various ways, such as using open-source software (for example, the P4 network programming language) or commercial modules or IP. Software offers tremendous flexibility, but can cost a bundle even if the latest standard development methods are used.
About the Organizer/Moderator:
John Lockwood is the CEO/founder of Algo-Logic, a developer of low-latency<br>networking for financial applications, data center networks, in-memory databases, and<br>real-time systems. The company´┐Ż€™s customers include international banks, trading<br>firms, and exchanges. Before founding Algo-Logic, he managed the NetFPGA project at<br>Stanford and was a professor at Washington University in St. Louis. He has also been a<br>consultant to SAIC on FPGA-accelerated networks. He has published over 100 papers<br>and patents on networking with FPGAs and served as principal investigator on many<br>government and corporate grants. He earned a PhD in Electrical and Computer<br>Engineering from the University of Illinois at Urbana/Champaign and has spoken at<br>many important conferences.

Wednesday, June 14th
03:10-4:10 PM
A-102: Networking Applications 1 - Telco Networks (Networking Track)
Moderator: Mario Baldi, Fellow, AMD

Paper Presenters:
Using SmartNICs to Accelerate Network Function Virtualization (NFV)
Geetha Jayagopi, Strategic Planner, Intel

Mirek Walukiewicz, Solution Architect, Intel
Using SmartNICs in 5G Networks
Awanish Verma, Director and Principal Architect, AMD

Session Description:
SmartNICs are a great fit for telco networks because they increase modularity and scability, both major assets for telcos. Typical tasks include network function virtualization (NFV, software-defined networking for telcos) and 5G mobile networks.
About the Organizer/Moderator:
Mario Baldi is a Fellow at AMD in Research and Advanced Development, where he works on APIs, software development environments, and new system-on-chips. He previously worked on product management at Pensando Systems and as Director of Technology at Cisco, where he helped develop the operating system for Nexus switches. He has over 25 years experience at the forefront of computer networking. He is also an Associate Professor of Information Processing Systems (currently on leave) at Politecnico di Torino (Technical University of Turin, Italy) and has held visiting professorships at universities in four continents. He earned a PhD in computer engineering from the Politecnico di Torino and is active in the Architecture Workgroup of the P4 networking language. He holds 35+ patents and has written over 150 technical publications and two books.

Wednesday, June 14th
03:10-4:10 PM
B-102: Storage/Security Applications (Data Centers Track)
Moderator: Donglai Dai, Chief Engineer, X-ScaleSolutions

Paper Presenters:
Protecting SmartNICs with Physical Unclonable Functions (PUFs)
Reed Hinkel, VP Business Development, Intrinsic ID

Implementing High-Speed Storage Solutions with SmartNICs and DPUs
Rob Davis, VP Storage, NVIDIA

DPUs and AI Protecting Legacy Storage Servers
Jemmee Yung, VP Business Development, BloomBase

Session Description:
Storage applications include SAN, NAS, and RAID, as well as standard utilities such as deduplication, encryption/decryption, mirroring, and other functions. SmartNICs can offload tasks from central processors, thus avoiding bottlenecks in networked systems. They can also promote modularity, scalability, and flexibility. Much of the storage management overhead can move to the SmartNICs, thus greatly simplifying the implementation of upgrades, revisions, and new policies. SmartNICs can also be used to implement system-wide views, such as software-defined storage, object storage, or networked filesystems. Security applications include deep packet inspection, firewalls, and defenses against denial-of-service (DDoS) attacks. SmartNICs isolate the security functions for easy updating or replacement, keep threats well away from central facilities, and assume overhead functions so compute units can spend their time doing customer applications. Of course, SmartNICs must themselves be protected like any other system component.
About the Organizer/Moderator:
Donglai Dai is Chief Engineer at X-ScaleSolutions, where he leads the company's R&D team. His current work focuses on developing and enhancing communication libraries, checkpointing and restart libraries, performance analysis tools for distributed and parallel HPC and deep learning applications on HPC systems and clouds. He is the principal investigator for several DOE SBIR grants and a member of the checkpoint restart standard steering committee. Before joining X-Scale Solutions, he worked at Intel, Cray, and SGI. He holds over 10 US patents and has published over 40 technical papers, presentations, or book chapters. He earned a PhD in computer science from Ohio State University.

Wednesday, June 14th
03:10-4:10 PM
C-102: Next Great Breakthrough in SmartNICs Panel (sponsored by Canonical) (Panels Track)
Moderator: Roy Chua, Principal, AvidThink

Panel Members:
Panelist: Jon Sreekanth, Architect, Achronix

Panelist: Eric Hibbard, Director Product Planning - Security, Samsung Semiconductor

Panelist: Frode Nordahl, Senior Engineer, Canonical

Session Description:
Many major changes will surely occur in the emerging SmartNIC arena. They include the addition of standard slots for GPUs and DPUs, faster processors, more canned applications (perhaps available via an app store), more standards, better operating system support, and greater use of processors other than Arm cores. Other possible advances could include the integration of on-board optics, higher frequency versions of Ethernet, the use of persistent memory, and the use of higher-speed interfaces such as CXL. A new form factor with a large power budget (such as the one suggested by SNIA) would be welcome as well.
About the Organizer/Moderator:
Roy Chua is Founder/Principal Analyst of AvidThink, where he covers covering cloud, telco, and technology infrastructure. He is a frequent conference participant and report writer. He has been quoted in many leading publications, including Wall Street Journal, FierceTelecom, FierceWireless, The New Stack, and Light Reading. Before founding AvidThink, he was co-founder/Chief Product Officer at SDxCentral, an independent B2B media company covering the technology infrastructure market. He has also been an executive in startups in software, software-defined networking, and networking. He earned an MSEE at UC Berkeley and an MBA at MIT.

Wednesday, June 14th
04:20-5:40 PM
A-103: Network Acceleration 2 - System Applications (Networking Track)
Moderator: Nabil Damouny, Chief Strategist, Autonomous Edge

Paper Presenters:
Removing the Tail from SmartNIC Latency
John Lockwood, CEO, Algo-Logic

High-Speed Secure Virtual Application Delivery Using FPGA-Based SmartNICs
Tim Michels, Distinguished Engineer, F5 Networks

Geetha Jayagopi, Strategic Planner, Intel
Using a SmartNIC to Recover Dropped Packets
Paul Borrill, CEO, Daedaelus

Session Description:
SmartNICs often have a great deal of processing power left after doing their primary tasks. This orphan processing power can serve many purposes, including recovery of dropped packets, low-latency networking, and virtual applications.
About the Organizer/Moderator:
Nabil Damouny is the Principal at Autonomous Edge Consulting, where he focuses on edge applications of SmartNICs. He was previously Sr Director Strategic Marketing at Netronome, where he worked on marketing and business development opportunities in networking, storage, and high-performance computing. He has also been a founder and VP Marketing at Basis Communications, a maker of network processors acquired by Intel. Earlier he worked at Intel in the CTO office of the Mobility Group. He has published over 25 technical and marketing papers, and is a frequent speaker at conferences. He has been active in many standards committees including IEEE802, IETF, and ISDN. Nabil earned a BSEE from IIT, and an MSECE from UC Santa Barbara. He holds three patents in computer architecture and remote networking.

Wednesday, June 14th
04:20-5:40 PM
B-103: Software 1 – Operating Systems (Software Track)
Moderator: Jan Zieleznicki, Sr Software Engineer, CodiLime

Paper Presenters:
SmartNIC-Based Approach to Implementing Networking on Cloud Servers
Avijit Gupta, , Microsoft

Michal Zygmunt, , Microsoft
Highly Secure OS Kernel for SmartNIC Applications
Paweł Dulęba, Senior Software Engineer, CodiLime

Provisioning and Commissioning a DPU at the Bare-Metal Level
Bjorn Tillenius, Software Engineer, Canonical

Frode Nordahl, Senior Engineer, Canonical

Session Description:
Operating systems play a large role in SmartNIC applications. The SmartNIC or DPU needs an operating system to run applications, but most Linux distributions are very large and contain features not used in devices that have a simple run-time environment. One solution is to use a minimal kernel specially designed for such situations. Another approach is to employ a bare-metal (unshared) server that dispenses with virtualization (no hypervisor).
About the Organizer/Moderator:


Wednesday, June 14th
04:20-5:40 PM
C-103: Optimizing SmartNIC Applications Panel (sponsored by Keysight) (Panels Track)
Moderator: Ahmet Houssein, CEO, SiPanda

Panel Members:
Panelist: T Sridhar, VP Architecture, Juniper Networks

Panelist: Venkat Pullela, Chief Technology Networking, Keysight Technologies

Panelist: Scott Schweitzer, Director - SmartNIC Product Planning, Achronix

Panelist: Donglai Dai, Chief Engineer, X-ScaleSolutions

Panelist: Andy Fingerhut, Principal Engineer, Intel

Session Description:
The usual issue is to get applications to run faster. One common problem is a slow network stack, so check around to see if yours is the latest version or team members or associates have found others to be more efficient. Other common approaches include replacing the processor with a faster model – some SmartNICs have chips that are way behind the state-of-the-art. Still other alternatives are replacing or upgrading the message passing mechanism that starts up the SmartNIC and moves its results – everything may be delayed if messages are not being generated or recognized efficiently. Some NICs even have internal features that offload or speed up message processing. Other system software may also run much faster if it executes at the network level rather than the host level. There are even tools available that can predict how large a performance gain you can expect from offloading.
About the Organizer/Moderator:
Ahmet Houssein is Founder/CEO of SiPanda, which is developing a new domain-specific CPU for cloud datacenters. His current areas of interest include CPUs and SoCs, as well as system-level solutions for clouds, servers, and storage. Before founding SiPanda, he was a Principal Semiconductor Industry Advisor for Amazon Web Services and worked for Xilinx, SolarFlare, QLogic and Intel. He delivered the industry’s first 25G Ethernet products to market and developed the top-performing and lowest-latency NVMe over TCP products. He also pioneered SmartNICs through a joint venture between SolarFlare and Xilinx and devised advanced architectures that provided the basis for chip-based storage solutions, PCIe, and symmetrical multiprocessing chiplets. He has headed two successful startups that were acquired. He earned a BSEE equivalent from London Colleges.