| Tuesday, June 13th |
Tuesday, June 13th
08:30-12:00 PM | | SONIC-DASH Workshop: Morning Session (Workshop Track) | | Organizer + Moderator: Kristina Moore, , Microsoft | Paper Presenters:
| | Session Description:
| "Part 1 – Morning – Overview of SONiC DASH What is it? Example of an application and the difference SONiC DASH makes (to show where we are heading and why the audience should want to come along) What problems is it intended to solve? What are typical applications? How do you use it? Panel: How do you make SONiC DASH work for your application?
| | About the Organizer/Moderator: |
|
|
Tuesday, June 13th
08:30-12:00 PM | | Pre-Conference Tutorial A: SmartNIC Basics (Pre-Conference Tutorials Track) | | Organizer + Moderator: Scott Schweitzer, Director - SmartNIC Product Planning, Achronix | Speaker(s):
| Speaker: Mario Baldi, Fellow, AMDSpeaker: Scott Schweitzer, Director - SmartNIC Product Planning, AchronixSpeaker: Rich Cahill, Data Center Acceleration Engineer, IntelSpeaker: Eyal Tokman, Director Software Engineering, NVIDIA | Session Description:
|
| | About the Organizer/Moderator: | Scott Schweitzer is Director - SmartNIC Product Planning at Achronix Semiconductor, where he helps define SmartNIC and data center accelerator products for FPGAs. He was previously a Technology Evangelist at Xilinx, where he focused on acceleration and helped customers and partners recognize new opportunities and define new innovative solutions. He has also produced the popular blogs TechnologyEvangelist.com and 10GbE.net, which received thousands of monthly page views, and written a series of three articles on SmartNICs for Electronic Design magazine. Before joining Xilinx, Scott worked at SolarFlare Communications, Myricom, NEC Solutions America, and IBM. He earned an MS in Computer Science from NYU’s Tandon School of Engineering.
|
|
Tuesday, June 13th
08:30-12:00 PM | | Special Tutorial on Generative AI Acceleration (Pre-Conference Tutorials Track) | | Moderator: Rob Davis, VP Storage, NVIDIA | Speaker(s):
| Speaker: Jean-Francois Lacasse, AI-on-5G Evangelist, NVIDIASpeaker: Amit Badlani, Sr Product Manager - Autonomous Vehicles, NVIDIASpeaker: Chris Arangio, Morpheus - AI for Cybersecurity, NVIDIASpeaker: Gilad Shainer, Sr VP Marketing, NVIDIASpeaker: Ashutosh Malegaonkar, Director - AI Enterprise, NVIDIA | Session Description:
|
| | About the Organizer/Moderator: |
|
|
Tuesday, June 13th
01:00-5:00 PM | | SONIC-DASH Workshop: Afternoon Session (Workshop Track) | | Organizer + Moderator: Kristina Moore, , MicrosoftModerator: Sanjay Thyamagundalu, Fellow, AMD | Paper Presenters:
| | Session Description:
| Part 2 - Applications: Networking Security Distributed Computing Telecom High-Performance Computing Panel: SONiC-Dash in 2025 and How We Got There (Short-Term Trends)
| | About the Organizer/Moderator: |
|
|
Tuesday, June 13th
01:00-5:00 PM | | Pre-Conference Tutorial B: SmartNICs Applications and Use Cases (Pre-Conference Tutorials Track) | | Organizer + Moderator: Rob Davis, VP Storage, NVIDIAOrganizer: Ahmet Houssein, CEO, SiPanda | Speaker(s):
| Speaker: Jon Sreekanth, Architect, AchronixSpeaker: Yuval Degani, Sr Director Software Engineering, NVIDIASpeaker: Donpaul Stephens, CEO, AirMettleSpeaker: Pradeep Nallimelli, Datacenter Solutions Architect, AMD | Session Description:
|
| | About the Organizer/Moderator: | As the leader of the global data center solutions architect team at AMD, Seong focuses on driving the development of data center application acceleration and offload solutions for computing, networking, and storage platforms. With over 25 years experience in the communications and data center industry and a strong background in networking infrastructure technology and market trends, Seong has a deep understanding of data center networking, storage, and compute solutions. He has recently focused on smart world solutions based on video analytics, machine learning, video transcoding, database acceleration, smartNICs, and storage accelerations. Seong earned a PhD in Electrical and Computer Engineering from Stony Brook University (NY). He has written many technical papers, academic papers, and whitepapers, holds patents, and has presented industry seminars and webinars.
Ahmet Houssein is Founder/CEO of SiPanda, which is developing a new domain-specific CPU for cloud datacenters. His current areas of interest include CPUs and SoCs, as well as system-level solutions for clouds, servers, and storage. Before founding SiPanda, he was a Principal Semiconductor Industry Advisor for Amazon Web Services and worked for Xilinx, SolarFlare, QLogic and Intel. He delivered the industry’s first 25G Ethernet products to market and developed the top-performing and lowest-latency NVMe over TCP products. He also pioneered SmartNICs through a joint venture between SolarFlare and Xilinx and devised advanced architectures that provided the basis for chip-based storage solutions, PCIe, and symmetrical multiprocessing chiplets. He has headed two successful startups that were acquired. He earned a BSEE equivalent from London Colleges.
|
|
Tuesday, June 13th
01:00-5:00 PM | | Pre-Conference Tutorial C: Open Programmable Infrastructure (OPI) (Pre-Conference Tutorials Track) | | Organizer: Paul Pindell, Biz Dev Principal Architect, F5 NetworksOrganizer: Manoj Roge, Independent Consultant, MarvellModerator: Joseph White, SIG Co-Chair, SNIA | Speaker(s):
| | Session Description:
| The Open Programmable Infrastructure (or OPI) is an open-source effort within the Linux Foundation to develop a standard API for utilizing SmartNICs, DPUs and IPUs, and other coprocessors or processing elements. It will allow users to provision and orchestrate all devices in the same way, thus allowing users to handle many different devices, implement new devices, and change or replace devices without learning a new command structure. It will also allow manufacturers to create a standard API, deliver new or upgraded devices faster, and benefit from a large ecosystem. It makes learning curves for new devices shorter and implementation or software errors easier to find. It opens new markets for devices and eliminates concerns over one-of-a-kind implementations.
| | About the Organizer/Moderator: | Paul Pindell is Principal Architect Business Development at F5, a multi-cloud application<br>services and security company. He oversees technical partnerships across F5’s<br>product portfolio. A frequent conference keynote and breakout speaker, he has<br>presented at Intel Innovation, Open Source Summit, Red Hat Tech Exchange, and<br>VMworld. He is the project founder, maintainer, and chair of the Outreach Committee<br>for the Open Programmable Infrastructure project, intended to provide a standard API<br>for SmartNICs, DPUs, and other coprocessor devices. His specialties include Kubernetes,<br>OpenShift, OpenStack, and software-defined networking (SDN). Before joining F5, he led<br>data center operations for Symantec’s Antivirus Response Data Centers and security software<br>testing laboratories. He earned an MBA at Bushnell University and holds several VMware certifications.
Manoj Roge is a product marketing and management professional specializing in AI, data center, and communications technologies. He previously led solutions planning<br>and marketing for CPU and DPU (Data Processing Unit) products at Marvell. He has also worked for Synopsys, Achronix, and Xilinx. His current interests are in CPU architecture, network processing, security, ASICs, and SmartNICs. He has presented at many conferences, including Design Automation Conference (DAC), Flash Memory Summit, Open Compute Project (OCP) Global Summit, and the International SoC Conference. He has also written articles and whitepapers and holds several patents. He earned an MSEE in VLSI Design from University of Texas at Arlington.
Joseph L. White is a Fellow with Dell’s CTO office focused on NVMe-oF, DPUs, networking, and disaggregated infrastructure. His wide-ranging interests include fabrics, automation, protocols, switches, and distributed systems. Previously he worked for Juniper Networks and NetApp, and was a co-founder of Nishan Systems, the first company to champion IP storage and deliver enterprise quality multi-protocol SAN switches, routers, and gateways. He has been active in many open source and standards groups, including being the Chair of the OPI’s Technical Steering Committee. He holds 17 patents.
|
|
Tuesday, June 13th
05:00-6:00 PM | | Superpanel: Making SmartNICs and DPUs into a Major Technology (Panels Track) | | Organizer: Paul Borrill, CEO, DaedaelusModerator: Bill Wong, Editor, Endeavor Business Media | Paper Presenters:
| | Session Description:
|
| | About the Organizer/Moderator: | Paul Borrill is founder and Chief Product Officer of Daedaelus and a leading industry expert on resilient network and storage infrastructures. He has been a major contributor to modern infrastructure development at such technology-leading companies and organizations as NASA, Apple, Sun Microsystems, and Quantum. Paul was cofounder of the Hot Interconnects conference and founding chair of the Storage Networking Industry Association (SNIA). Paul was also VP Technical Activities and VP Standards for the IEEE Computer Society, the leading worldwide technical society for computer engineering. Paul earned a PhD in Physics from University College London. He has presented at many conferences on distributed systems and holds nine patents in that area.
Bill Wong is Editor of Electronic Design Magazine, as well as Senior Content Director of its parent organization, Endeavor Business Media. One of the best-known editors in the technical press, he is noted for his interviews, analysis, and project articles. He focuses on embedded, software, and systems applications in the magazine. He has solid technical credentials, having earned a BSEE at Georgia Tech and an MSCS at Rutgers. He still works on hardware and software projects, including C, C++, and PHP programming and hardware ranging from robotics to AI systems.
|
|
Tuesday, June 13th
06:00-8:30 PM | | Chat with the Experts (Pre-Conference Tutorials Track) | | Expert Table Leaders:
| High Performance Computing
Addison Snell, CEO, Intersect360 ResearchSONiC-DASH
Gerald DeGrace, Head Project Manager for Azure Disaggregated Technologies and DASH Open Source, MicrosoftTesting
Mircea Dan Gheorghe, Director System Test, Keysight TechnologiesSmartNICs Summit 2024 Ideas
Chuck Sobey, General Chair, SmartNICs SummitProcessors
Biren Mehta, Director Network & Edge Infrastructure, ArmNetwork Acceleration
Deb Chatterjee, Network Acceleration Team Lead, IntelSoftware
Pawel Duleba, Sr Software Engineer, CodiLimeApplication Acceleration
Awanish Verma, Principal System Architect, AMDMarket Research
Baron Fung, Research Director, Dell'Oro GroupDistributed Computing
Paul Borrill, CEO, DaedaelusDPUs
Rob Davis, VP Storage, NVIDIAFPGA-Based Devices
Mohan Krishnareddy, System Architect, AchronixAI/ML Applications
Mario Baldi, Fellow, AMDOpen Programmable Infrastructure (OPI)
Manoj Roge, Independent Consultant, Marvell | Session Description:
|
| | About the Organizer/Moderator: | |
|