| Tuesday, June 13th |
Tuesday, June 13th
08:30-12:00 PM | | SONIC-DASH Workshop: Morning Session (Workshop Track) | | Paper Presenters:
| Shift Left Testing & Importance of a Behavioral Model/Hardware Testing at Scale
Mircea Dan Gheorghe, Director System Test, Keysight TechnologiesChris Sommers,
Software Architect,
Keysight Technologies
DASH Programmability, and SmartSwitch Use Case
Paul Cummins, , NVIDIAIntro to DASH (Disaggregated APIs for SONiC Hosts) - Click for Proceedings:
Kristina Moore, Principal Product Manager, Microsoft | Session Description:
| SONiC-DASH is open-source software intended to deliver enterprise network performance to critical cloud applications using the latest SmartNICs, DPUs, IPUs, accelerators, and network appliances. It provides a structure for using the devices to perform protocol offload, network and application acceleration, and many other tasks. It provides standard ways for system developers and administrators to install, deploy, orchestrate, administer, monitor, update, and remove devices. The intent is to make SmartNICs and DPUs easier to use, thus allowing their deployment in enterprise networks, clouds, supercomputers, high-performance computing, IoT, factory networks, and other installations. It provides a framework for administration, monitoring, and repair. It thus allows administrators to utilize external processing elements to offload CPUs and accelerate tasks such as AI/ML, analytics, deep packet inspection, media and signal processing, virtual reality, and scientific and military applications. It also offers interoperable APIs that permit administrators to introduce new devices without undergoing long learning curves or having to maintain multiple interfaces.
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Tuesday, June 13th
08:30-12:00 PM | | Pre-Conference Tutorial A: SmartNIC Basics (Pre-Conference Tutorials Track) | | Organizer + Moderator: Scott Schweitzer, Director SmartNIC Product Planning, Achronix | Speaker(s):
| Speaker: Mario Baldi, Fellow, AMDSpeaker: Scott Schweitzer, Director SmartNIC Product Planning, AchronixSpeaker: Rich Cahill, Data Center Acceleration Engineer, IntelSpeaker: Eyal Tokman, DPU Architect, NVIDIA | Session Description:
| SmartNICs are a major new technology that brings edge and distributed processing to networks. They have their own onboard compute, which can run tasks ranging from protocol offload to traffic steering and application-specific use cases. SmartNICs reduce the burden on central processors, allowing them to focus on their primary functions rather than networking tasks. They can also accelerate applications that require extra computing power, such as AI/ML, analytics, or security. The result is faster, more scalable, and more modular networks better suited to today’s clouds and data centers. SmartNICs are now available with several architectures. The major difference is in the processing elements. ASIC and FPGA-based devices run tasks at hardware speed but have limited flexibility. Processor-based devices are slower but can do almost anything as long as software is available or can be developed. The software framework and development platforms have become critical components that users must consider when building a solution.
| | About the Organizer/Moderator: | Scott Schweitzer is Director - SmartNIC Product Planning at Achronix Semiconductor, where he helps define SmartNIC and data center accelerator products for FPGAs. He was previously a Technology Evangelist at Xilinx, where he focused on acceleration and helped customers and partners recognize new opportunities and define new innovative solutions. He has also produced the popular blogs TechnologyEvangelist.com and 10GbE.net, which received thousands of monthly page views, and written a series of three articles on SmartNICs for Electronic Design magazine. Before joining Xilinx, Scott worked at SolarFlare Communications, Myricom, NEC Solutions America, and IBM. He earned an MS in Computer Science from NYU’s Tandon School of Engineering.
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Tuesday, June 13th
08:30-12:00 PM | | Special Tutorial on Generative AI Acceleration (presented by NVIDIA) (Pre-Conference Tutorials Track) | | Speaker(s):
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| Generative AI applications, such as the immensely popular ChatGPT®, are currently the talk of the entire technical world with millions signing up to preview them and create both a huge variety of uses and a large ecosystem. However, everyone knows that such applications, with their large language models and huge databases, will take enormous amounts of computing power at tremendous expense. Low-cost acceleration will be a key to making their use viable. Surely, SmartNICs, DPUs, and IPUs can provide order-of-magnitude increases in compute-per-dollar. Major efforts will be necessary to identify the most productive approaches along with ways to make implementation in low-cost systems much faster and easier. Everyone expects AI to have millions of users and a large ecosystem in record time. However, the industry also agrees that these applications will challenge existing compute resources, causing high costs and long run times. This tutorial will describe and demonstrate NVIDIA technologies that help address these challenges
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Tuesday, June 13th
01:00-5:00 PM | | SONIC-DASH Workshop: Afternoon Session (Workshop Track) | | Paper Presenters:
| SDN, Disaggregation, and DASH
Michal Zygmunt, Cloud Architect, MicrosoftAvijit Gupta,
Principal Software Engineering Manager,
Microsoft
Panel: SONiC-Dash in 2025 and How We Got There (Short- Term Trends)
Sanjay Thyamagundalu, Fellow, AMDMichal Zygmunt,
Cloud Architect,
Microsoft
Avijit Gupta,
,
Microsoft
High Availability (HA)
Sanjay Thyamagundalu, Fellow, AMD | Session Description:
| SONiC-DASH is open-source software intended to deliver enterprise network performance to critical cloud applications using the latest SmartNICs, DPUs, IPUs, accelerators, and network appliances. It provides a structure for using the devices to perform protocol offload, network and application acceleration, and many other tasks. It provides standard ways for system developers and administrators to install, deploy, orchestrate, administer, monitor, update, and remove devices. The intent is to make SmartNICs and DPUs easier to use, thus allowing their deployment in enterprise networks, clouds, supercomputers, high-performance computing, IoT, factory networks, and other installations. It provides a framework for administration, monitoring, and repair. It thus allows administrators to utilize external processing elements to offload CPUs and accelerate tasks such as AI/ML, analytics, deep packet inspection, media and signal processing, virtual reality, and scientific and military applications. It also offers interoperable APIs that permit administrators to introduce new devices without undergoing long learning curves or having to maintain multiple interfaces.
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Tuesday, June 13th
01:00-5:00 PM | | Pre-Conference Tutorial B: SmartNICs Applications and Use Cases (Pre-Conference Tutorials Track) | | Organizer + Moderator: Rob Davis, VP Storage, NVIDIAOrganizer: Ahmet Houssein, CEO, SiPanda | Speaker(s):
| Speaker: Jon Sreekanth, Architect, AchronixSpeaker: Yuval Degani, Sr Director Software Engineering, NVIDIASpeaker: Donpaul Stephens, CEO, AirMettleSpeaker: Pradeep Nallimelli, Datacenter Solutions Architect, AMD | Session Description:
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| | About the Organizer/Moderator: | As the leader of the global data center solutions architect team at AMD, Seong focuses on driving the development of data center application acceleration and offload solutions for computing, networking, and storage platforms. With over 25 years experience in the communications and data center industry and a strong background in networking infrastructure technology and market trends, Seong has a deep understanding of data center networking, storage, and compute solutions. He has recently focused on smart world solutions based on video analytics, machine learning, video transcoding, database acceleration, smartNICs, and storage accelerations. Seong earned a PhD in Electrical and Computer Engineering from Stony Brook University (NY). He has written many technical papers, academic papers, and whitepapers, holds patents, and has presented industry seminars and webinars.
Ahmet Houssein is Founder/CEO of SiPanda, which is developing a new domain-specific CPU for cloud datacenters. His current areas of interest include CPUs and SoCs, as well as system-level solutions for clouds, servers, and storage. Before founding SiPanda, he was a Principal Semiconductor Industry Advisor for Amazon Web Services and worked for Xilinx, SolarFlare, QLogic and Intel. He delivered the industry’s first 25G Ethernet products to market and developed the top-performing and lowest-latency NVMe over TCP products. He also pioneered SmartNICs through a joint venture between SolarFlare and Xilinx and devised advanced architectures that provided the basis for chip-based storage solutions, PCIe, and symmetrical multiprocessing chiplets. He has headed two successful startups that were acquired. He earned a BSEE equivalent from London Colleges.
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Tuesday, June 13th
01:00-5:00 PM | | Pre-Conference Tutorial C: Open Programmable Infrastructure (OPI) (Pre-Conference Tutorials Track) | | Organizer: Paul Pindell, Biz Dev Principal Architect, F5 NetworksOrganizer: Manoj Roge, , ConsultantModerator: Joseph White, TSE Chair, Open Programmable Infrastructure (OPI) | Speaker(s):
| Presenter: Dong Wei, Standards Architect, ArmPresenter: Venkat Pullela, Chief Of Technology, Networking, Keysight TechnologiesPresenter: Vipin Jain, Sr Fellow Engineer, AMDPresenter: Mark Sanders, Distinguished Engineer, Dell | Session Description:
| The Open Programmable Infrastructure (or OPI) is an open-source effort within the Linux Foundation to develop a standard API for utilizing SmartNICs, DPUs and IPUs, and other coprocessors or processing elements. It will allow users to provision and orchestrate all devices in the same way, thus allowing users to handle many different devices, implement new devices, and change or replace devices without learning a new command structure. It will also allow manufacturers to create a standard API, deliver new or upgraded devices faster, and benefit from a large ecosystem. It makes learning curves for new devices shorter and implementation or software errors easier to find. It opens new markets for devices and eliminates concerns over one-of-a-kind implementations.
| | About the Organizer/Moderator: | Paul Pindell is Principal Architect Business Development at F5, a multi-cloud application<br>services and security company. He oversees technical partnerships across F5’s<br>product portfolio. A frequent conference keynote and breakout speaker, he has<br>presented at Intel Innovation, Open Source Summit, Red Hat Tech Exchange, and<br>VMworld. He is the project founder, maintainer, and chair of the Outreach Committee<br>for the Open Programmable Infrastructure project, intended to provide a standard API<br>for SmartNICs, DPUs, and other coprocessor devices. His specialties include Kubernetes,<br>OpenShift, OpenStack, and software-defined networking (SDN). Before joining F5, he led<br>data center operations for Symantec’s Antivirus Response Data Centers and security software<br>testing laboratories. He earned an MBA at Bushnell University and holds several VMware certifications.
Manoj Roge is a product marketing and management professional specializing in AI, data center, and communications technologies. He previously led solutions planning<br>and marketing for CPU and DPU (Data Processing Unit) products at Marvell. He has also worked for Synopsys, Achronix, and Xilinx. His current interests are in CPU architecture, network processing, security, ASICs, and SmartNICs. He has presented at many conferences, including Design Automation Conference (DAC), Flash Memory Summit, Open Compute Project (OCP) Global Summit, and the International SoC Conference. He has also written articles and whitepapers and holds several patents. He earned an MSEE in VLSI Design from University of Texas at Arlington.
Joseph L. White is a Fellow with Dell’s CTO office focused on NVMe-oF, DPUs, networking, and disaggregated infrastructure. His wide-ranging interests include fabrics, automation, protocols, switches, and distributed systems. Previously he worked for Juniper Networks and NetApp, and was a co-founder of Nishan Systems, the first company to champion IP storage and deliver enterprise quality multi-protocol SAN switches, routers, and gateways. He has been active in many open source and standards groups, including being the Chair of the OPI’s Technical Steering Committee. He holds 17 patents.
Speaker Bio: Joseph L. White is a Fellow with Dell’s CTO office focused on NVMe-oF, DPUs, networking, and disaggregated infrastructure. His wide-ranging interests include fabrics, automation, protocols, switches, and distributed systems. Previously he worked for Juniper Networks and NetApp, and was a co-founder of Nishan Systems, the first company to champion IP storage and deliver enterprise quality multi-protocol SAN switches, routers, and gateways. He has been active in many open source and standards groups, including being the Chair of the OPI’s Technical Steering Committee. He holds 17 patents.
Speaker Bio: Venkat Pullela is Chief of Technology, Networking for Keysight Technologies, where he focuses on open, software-defined networking, and evolving testing architectures. He was previously Co-Founder at OpenNets, developing tools for programmable networks and SDN solutions. He has also worked at Broadcom as a Distinguished Engineer and at Cisco as a Sr. Director of Engineering. He has been an invited speaker at ONF Connect, OCP, and SIGCOMM events. He holds 25 patents. He earned an MS in CS from the Indian Institute of Technology Kanpur.
Speaker Bio: Joseph L. White is a Fellow with Dell’s CTO office focused on NVMe-oF, DPUs, networking, and disaggregated infrastructure. His wide-ranging interests include fabrics, automation, protocols, switches, and distributed systems. Previously he worked for Juniper Networks and NetApp, and was a co-founder of Nishan Systems, the first company to champion IP storage and deliver enterprise quality multi-protocol SAN switches, routers, and gateways. He has been active in many open source and standards groups, including being the Chair of the OPI’s Technical Steering Committee. He holds 17 patents.
Speaker Bio: Joseph L. White is a Fellow with Dell’s CTO office focused on NVMe-oF, DPUs, networking, and disaggregated infrastructure. His wide-ranging interests include fabrics, automation, protocols, switches, and distributed systems. Previously he worked for Juniper Networks and NetApp, and was a co-founder of Nishan Systems, the first company to champion IP storage and deliver enterprise quality multi-protocol SAN switches, routers, and gateways. He has been active in many open source and standards groups, including being the Chair of the OPI’s Technical Steering Committee. He holds 17 patents.
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Tuesday, June 13th
05:00-6:00 PM | | Superpanel: Making SmartNICs and DPUs into a Major Technology (Panels Track) | | Organizer: Paul Borrill, CEO, DaedaelusModerator: Bill Wong, Editor, Endeavor Business Media | Paper Presenters:
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| | About the Organizer/Moderator: | Paul Borrill is founder and Chief Product Officer of Daedaelus and a leading industry expert on resilient network and storage infrastructures. He has been a major contributor to modern infrastructure development at such technology-leading companies and organizations as NASA, Apple, Sun Microsystems, and Quantum. Paul was cofounder of the Hot Interconnects conference and founding chair of the Storage Networking Industry Association (SNIA). Paul was also VP Technical Activities and VP Standards for the IEEE Computer Society, the leading worldwide technical society for computer engineering. Paul earned a PhD in Physics from University College London. He has presented at many conferences on distributed systems and holds nine patents in that area.
Bill Wong is Editor of Electronic Design Magazine, as well as Senior Content Director of its parent organization, Endeavor Business Media. One of the best-known editors in the technical press, he is noted for his interviews, analysis, and project articles. He focuses on embedded, software, and systems applications in the magazine. He has solid technical credentials, having earned a BSEE at Georgia Tech and an MSCS at Rutgers. He still works on hardware and software projects, including C, C++, and PHP programming and hardware ranging from robotics to AI systems.
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Tuesday, June 13th
06:00-8:30 PM | | Chat with the Experts (Pre-Conference Tutorials Track) | | Expert Table Leaders:
| Testing
Mircea Dan Gheorghe, Director System Test, Keysight TechnologiesSmartNICs Summit 2024 Ideas
Chuck Sobey, General Chair, SmartNICs SummitSONiC-DASH
Gerald DeGrace, Head Project Manager for Azure Disaggregated Technologies and DASH Open Source, MicrosoftOpen Programmable Infrastructure (OPI)
Manoj Roge, , ConsultantHigh Performance Computing
Addison Snell, CEO, Intersect360 ResearchDPUs
Rob Davis, VP Storage, NVIDIAMarket Research
Baron Fung, Research Director, Dell'Oro GroupProcessors
Biren Mehta, Director Network & Edge Infrastructure, ArmNetwork Acceleration
Deb Chatterjee, Network Acceleration Team Lead, IntelApplication Acceleration
Awanish Verma, Principal System Architect, AMDDistributed Computing
Paul Borrill, CEO, DaedaelusSoftware
Pawel Duleba, Sr Software Engineer, CodiLimeFPGA-Based Devices
Mohan Krishnareddy, System Architect, AchronixAI/ML Applications
Mario Baldi, Fellow, AMD | Session Description:
| The session allows attendees to meet top experts in many crucial areas and ask questions in an informal setting. Each table has a different subject, and attendees are welcome to move from table to table. Beer, wine, soft drinks, and pizza are served to promote the informal atmosphere and encourage networking. Emphasis is on frequently asked questions, best practices, hints and warnings, major issues, and key products and standards.
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