Thursday, April 28th
Thursday, April 28th
9:00 AM-
A-201: System Development (Architectures/Software/Tools Track)
Moderator: Andrei Warkentin, ARM Enablement Architect, VMware

Paper Presenters:
Simplifying SmartNIC System Testing - Click for Proceedings:
Razvan Stan, Sr Engineering Manager, Keysight Technologies

Leveraging P4 in SmartNICs: Expected Benefits, Challenges, and Solutions - Click for Proceedings:
Mario Baldi, Fellow, Pensando Systems

Session Description:
System development for SmartNICs is a difficult process. Developers for any new technology always face a lack of widely available, mature platforms. Such platforms usually include a wide range of tools such as programming languages and test tools. Open-source projects provide further examples. However, it is generally up to the development team to find the tools and make them work together for stages from problem definition through debug and test.
About the Organizer/Moderator:
Andrei Warkentin is an Arm Enablement Architect at VMware, where he is the Technical Lead for the ESXi-ARM team which conducts advanced development of vSphere hypervisor technology for the 64-bit Arm architecture. He is an architect for Project Monterey, an extension of VMware Cloud Foundation (VCF) using SmartNICs to improve performance, implement zero-trust security, and simplify operations across data center, edge, and cloud applications. He has worked on a wide range of issues related to Arm enablement and strategy, ranging from low-level hypervisor design and implementation to product definition and partner and ecosystem engagement. Before joining VMware, he worked at Motorola Mobility on Google Experience devices and at Microsoft on Hyper-V and UEFI projects. He earned a BS in computer science from the University of Illinois Chicago. He holds 38 patents and has three publications.

Thursday, April 28th
9:00 AM-
B-201: Open Networking (Edge/Data Center Applications Track)
Moderator: Nabil Damouny, Principal, Autonomous Edge

Paper Presenters:
Extending DPUs to Enable Software-Defined I/O (SDIO) - Click for Proceedings:
Dhaval Parikh, Director Segment Marketing, Arm

DPUs in Open Infrastructure Deployments - Click for Proceedings:
Frode Nordahl, Sr Engineer, Canonical

Dmitry Shcherbakov, Sr Engineer, Canonical

Session Description:
Open networking approaches are an obvious foundation on which to develop SmartNIC applications. They provide ways to define infrastructure in software rather than in hard-to-change and usually proprietary hardware. However, such approaches often create a lot of management overhead that can slow down systems significantly. Data processing units (DPUs) are a new way to handle the overhead without causing system saturation, keeping it totally away from central processors. New approaches and new software versions also become much easier to implement.
About the Organizer/Moderator:
Nabil Damouny is the Principal at Autonomous Edge Consulting, where he focuses on edge applications using SmartNICs in a wide variety of areas. He was previously Sr Director of Strategic Marketing at Netronome, where he worked on marketing and business development opportunities in networking, storage, and high-performance computing. He has also been a founder and VP Marketing at Basis Communications, a maker of network processors which was acquired by Intel. Earlier he worked at Intel in the CTO office of the Mobility Group. He has published over 25 technical and marketing papers, and is a frequent speaker at conferences. He took active part in many standard committees including ATM Forum, FDDI, IEEE802, IETF, and ISDN. Nabil earned a BSEE from IIT in Chicago, and an MSECE from UC Santa Barbara. He holds three patents in computer architecture and remote networking.

Thursday, April 28th
9:00 AM-
C-201: Panel on Best Architecture for SmartNICs Today (sponsored by Marvell) (Panels Track)
Session Sponsor: Marvell
Moderator: Jim Harrison, Editor-in-Chief, Lincoln Technology Communications

Panel Members:
Panelist: Jim Finnegan, Sr VP Engineering, Netronome

Panelist: Derek Chickles, Director Machine Learning, Marvell

Panelist: Rob Davis, VP Storage, NVIDIA

Panelist: John Lockwood, CEO, Algo-Logic

Panelist: Wael Noureddine, Chief Architect, Fungible

Session Description:
Current SmartNIC architectures offer many tradeoffs. Ones based on ASICs or FPGAs are generally faster and easier to implement. Those based on standard processors are more flexible and easier to update. Coprocessors such as GPUs or DPUs increase performance but are expensive and difficult to program. Most observers expect the software-based devices to dominate the market because of their flexibility, but performance issues could leave a substantial market for hardware-based SmartNICs. The cost and time requirements for developing typical applications for processor-based SmartNICs is as yet unknown, but could have a big effect.
About the Organizer/Moderator:
Jim Harrison is the Editor-in-Chief at Lincoln Technology Communications and the author of many papers for numerous technology companies covering design of electronic systems and devices and providing interesting content on electronic components. He has written about everything from the latest gadgets to in-depth circuit design ideas. He spent 12 years as West Coast Editor for Electronic Products Magazine, where he covered a broad spectrum of technology ranging from ICs to passive components and design tools. Before that, he was an engineer for networking and telecom companies.

Thursday, April 28th
2:30 PM-
A-202: Edge Computing (Edge/Data Center Applications Track)
Moderator: Nabil Damouny, Principal, Autonomous Edge

Paper Presenters:
SmartNIC Architecture for Distributed Services at the Network Edge - Click for Proceedings:
Mario Baldi, Fellow, Pensando Systems

Advantages and Use Cases for Adding the CXL interface to DPUs - Click for Proceedings:
Pavel Shamis, Sr Principal Research Engineer, Arm

DPUs Help Systems Process Huge Data - Click for Proceedings:
Guru Bachchu, Lead Applications Engineer, Kalray

Session Description:
Edge computing means that a great deal of required processing occurs at the system edge, near where the data enters and leaves the system. The result is less traffic on buses and smaller burden on central compute units. However, such approaches do require extensive development of applications, high-speed interfaces at the edge, and often special chips such as DPUs that take over routine tasks. Programs and data must be provided to the edge processors, and results must be obtained from them. This all requires a communications system that is robust, fast, and easy-to-use.
About the Organizer/Moderator:
Nabil Damouny is the Principal at Autonomous Edge Consulting, where he focuses on edge applications using SmartNICs in a wide variety of areas. He was previously Sr Director of Strategic Marketing at Netronome, where he worked on marketing and business development opportunities in networking, storage, and high-performance computing. He has also been a founder and VP Marketing at Basis Communications, a maker of network processors which was acquired by Intel. Earlier he worked at Intel in the CTO office of the Mobility Group. He has published over 25 technical and marketing papers, and is a frequent speaker at conferences. He took active part in many standard committees including ATM Forum, FDDI, IEEE802, IETF, and ISDN. Nabil earned a BSEE from IIT in Chicago, and an MSECE from UC Santa Barbara. He holds three patents in computer architecture and remote networking.

Thursday, April 28th
2:30 PM-
B-202: Panel on SmartNIC Standards: What Is Needed Today?(sponsored by Keysight) (Panels Track)
Session Sponsor: Keysight Technologies
Moderator: Kimball Brown, Analyst, Analyst

Panel Members:
Panelist: Dong Wei, Standards Architect, Arm

Panelist: Joe White, Fellow, Dell

Panelist: Vipin Jain, CTO, Pensando Systems

Panelist: Venkat Pullela, Chief of Technology, Keysight Technologies

Session Description:
SmartNICs are currently not standardized at all. Each vendor has its own architectures, programming methods, and APIs. Obviously, customers have a difficult time deciding what they need and determining a clear path forward. What steps must be taken to improve the situation without limiting options or forcing choices before there is enough evidence to proceed? Is a new organization necessary or is it better to work within an existing one to reduce overhead costs? Several frameworks have already been suggested by vendors and academic researchers. Where do they fit into the picture?
About the Organizer/Moderator:
Kimball Brown is a Senior Alliances Advisor for the security software firm BlackRidge Technology. He was previously a Global Technical Strategist at VMware, where he engaged Cisco in co-development projects. He has also been a VP/Sr Datacom Analyst with LightCounting, a specialist group focused on high-speed interfaces and communications devices. He has experience with Broadcom and Dataquest as well. He earned an MBA from UC Berkeley and a BSEE from Duke University.

Thursday, April 28th
2:30 PM-
C-202: Academic Session (Academic Track)
Moderator: Ming Liu, Assistant Professor, University of Wisconsin - Madison

Paper Presenters:
NanoPU: A Nanosecond Network Stack for Data Centers - Click for Proceedings:
Stephen Ibanez, Researcher, Intel

Gimbal: Enabling Multi-tenant Storage Disaggregation on SmartNIC JBOFs - Click for Proceedings:
Jaehong Min, Graduate Student, University of Washington

FlexTOE: Flexible TCP Offload with Fine-Grained Parallelism - Click for Proceedings:
Rajath Shashidhara, Graduate Student, University of Washington

PANIC: A High-Performance NIC for Multi-Tenant Networks - Click for Proceedings:
Jiaxin Lin, Graduate Student, University of Texas - Austin

Session Description:
Academic research in SmartNICs has progressed rapidly in the past few years. There are many interesting contributions in the following general areas: . Architectures . Transport . Application Services . Programming Language Support Industry will surely find many of these projects to be of immediate interest to them for both ideas and personnel.
About the Organizer/Moderator:
Ming Liu is an Assistant Professor in the Computer Sciences Department at the University of Wisconsin – Madison. His research covers networking and systems, with a focus on network-based hardware acceleration. His projects include NVMe-oF targets for SmartNIC JBOFs, using SmartNICs to accelerate distributed transaction processing and offload actor-based distributed applications, and developing automated offloading insight for SmartNICs and using a data-flow based programing system for developing SmartNIC applications. He earned his PhD at the University of Washington and was a postdoctoral researcher at VMware. He has 11 published conference papers.

Thursday, April 28th
4:00 PM-
A-203: DPU's (Architectures/Software/Tools Track)
Moderator: Dong Wei, Standards Architect, Arm

Paper Presenters:
Server Networking Solutions Using DPUs
John Kim, Director Storage Marketing, NVIDIA

Offloading Networking and Security Overhead to Nearby DPUs
Vikram Singh, Sr Product Line Manager, Juniper Networks

Session Description:
DPUs can take over many time-consuming tasks in networked systems, thus reducing bus traffic and burdens on central processors. DPUs can be located near the network’s edge, thus putting them directly in the path between the network and central computing facilities. Such approaches also make processing easy to change or upgrade, requiring only changes in the DPU software.
About the Organizer/Moderator:
Dong Wei is a Lead Standards Architect and Fellow at Arm. He leads the Arm SystemReady Program. He has significant experience in leading the industry in innovations and standardization. He is the Vice President (Chief Executive) of the UEFI Forum and co-chairs its ACPI Working Group. He is a Board member of the PCI SIG and co-chairs its Firmware Working Group. He is a Board member and the Secretary of the CXL Consortium. He is a member of the Incubation Committee at the OCP Foundation. He is a Senior Member of IEEE. Before joining Arm, Wei was VP/Fellow at Hewlett-Packard and Hewlett Packard Enterprise (HPE). As the Chief Architect for UEFI and ACPI, he led the definitions of the interfaces of hardware, firmware, and operating systems for x64, x86, Arm, ia64, RISC-V and PA-RISC based systems. He earned an MSEE from the University of Idaho and an MBA from California State University - Sacramento. He has five published articles.

Thursday, April 28th
4:00 PM-
B-203: Panel on SmartNICs in 2027 & How We Got There (sponsored by X-Scale) (Panels Track)
Session Sponsor: X-ScaleSolutions
Moderator: Jim Finnegan, Sr VP Engineering, Netronome

Panel Members:
Panelist: Baron Fung, Director, Dell'Oro Group

Panelist: DK Panda, Professor, Ohio State University

Panelist: Scott Schweitzer, Sr Manager Product Planning, Achronix

Panelist: Manoj Roge, HPC / Data Center Segment Lead, Synopsys

Session Description:
The five-year horizon for SmartNICs is very promising. They will make up an ever increasing part of the NIC market, as their cost is more than balanced by the tremendous capabilities they bring to networked systems. More canned software will be available for them, as well as development platforms, operating systems, utilities, and other tools. Standardization will be a major issue, as most large customers will want multiple sources as well as large ecosystems and wide support for both development and test. Other issues include achieving higher throughput and lower latency, isolating executing applications from one another, security, and operating system support.
About the Organizer/Moderator:
Jim Finnegan is COO at Netronome, a maker of network processors and SmartNICs. Before joining Netronome, he worked at Intel, where he was general manager of both the Network Processor Division and the Communication Infrastructure Group's Technology Office. He has over 30 years' experience in the networks and communications businesses, including positions at Digital Equipment and Tellabs. He earned Bachelor's and Master's degrees in electronic engineering from Queen's University Belfast (Northern Ireland).