Wednesday, April 27th
Wednesday, April 27th
9:00 AM-
Plenary: SmartNICs - Where We Are Today (Plenary Track)
Paper Presenters:
Session Description:
SmartNICs, network interface cards with their own processing power and memory, have quickly become a major growth area in the NIC market. They allow system designers to offload tasks to their on-board processors, reducing the overhead burden on central processing units. Such offload has become important as network speeds increase and protocols become more complex. SmartNICs vary in architecture, with their processing power being implemented in ASICs, FPGAs, network processors, or standard processors. On-board processors obviously require software development, for which many tools (including the P4 networking language) are widely available. Applications have also increased, now including AI/ML, databases, storage tasks, security tasks, and protocol acceleration as well as basic protocol offload. Trends include packaged applications, on-board data or storage processors, special software stacks, and an even wider range of applications, platforms, and tools.
About the Organizer/Moderator:
Wednesday, April 27th
2:00 PM-
A-101: Architectures (Architectures/Software/Tools Track)
Moderator: Itay Ozery, Director Product Management, NVIDIA

Paper Presenters:
Practical Challenges in Building SmartNICs Using Massively Parallel Cores - Click for Proceedings:
Steve Zagorianakos, Chief Silicon Architect, Netronome

Johan Tonsing, Chief Architect, Netronome
Upgrading Data Centers with Data Processing Units (DPUs)
Itay Ozery, Director Product Management, NVIDIA

A Fourth-Generation Architecture for SmartNICs - Click for Proceedings:
Niel Viljoen, Chief Executive Officer & Founder, Netronome

Jim Finnegan, Sr VP Engineering, Netronome

Session Description:
SmartNIC architectures vary mainly in the implementation of their processing elements. Some use ASICs or FPGAs to achieve high hardware speeds at the cost of imited programmability. Others use general-purpose processors, most often ARM or RISC-V. The result is lower speed, but easier updating or reprogramming. The cost and time consumption of software development is a further issue. Combinations are possible, such as a RISC core included in an ASIC or FPGA or a processor-FPGA pairing, and still others utilize an extended computing unit such as a GPU, a data or storage processor (DPU), a network processor, or an AI chip.
About the Organizer/Moderator:
Itay Ozery is director of product marketing for networking at NVIDIA. He drives strategic product marketing and product management initiatives for data center and cloud networking solutions, with an emphasis on software-defined, hardware-accelerated approaches. Before joining NVIDIA, Itay worked on developing call center software and hardware for NICE Systems. Itay has led large-scale business and projects aimed at IT systems, networking, and cybersecurity for data centers and telecom service providers. He is an active blogger, Webinar presenter, and conference speaker.

Coming soon..

Speaker Bio: Steve Zagorianakos is the Chief Silicon Architect at Netronome, where he has led the development of four generations of high performance Network Flow Processors (NFP). He has been responsible for all aspects of silicon development, including product definition and architecture, logic design, pre-silicon verification, emulation, physical implementation, and post-silicon verification. Before joining Netronome, Steve was a silicon architect in the networking division at Intel, where he was responsible for the implementation and microarchitecture of several network processors. Steve holds many patents in processor architecture. He earned a BSEE from the University of Massachusetts Lowell.

Speaker Bio: Niel Viljoen is the founding CEO of Netronome, a leading developer of network processors and SmartNICs. A technology and business visionary, he has led the company in developing X86 networking co-processing solutions, resulting in significant revenue growth. Before founding Netronome, Niel was Group CTO for Marconi and GM/Sr VP of Fore Systems' Service Provider Business Unit, where he drove a highly successful ATM adapter and switch portfolio of products. Niel received his undergraduate degree from the University of Stellenbosch (South Africa) and is a post graduate from Cambridge University (UK).

Wednesday, April 27th
2:00 PM-
B-101: Data Center Applications (Edge/Data Center Applications Track)
Moderator: Pradeep Sindhu, CEO, Fungible

Paper Presenters:
eFPGAs Bring the Advantages of Programmable Logic to SmartNICs - Click for Proceedings:
Ralph Grundler, Sr Director Marketing, Flex-Logix

Handling Data-Centric Workloads with DPU-Based Accelerators
Pradeep Sindhu, CEO, Fungible

Building Hardware-Accelerated Networking Applications on SmartNICs - Click for Proceedings:
John Lockwood, CEO, Algo-Logic

John Hagerman, VP Marketing, Algo-Logic

Session Description:
SmartNICs can be useful in a wide variety of data center applications. The most common use case is handling protocol overhead. However, they can also serve other purposes, such as: Encryption/decryption Storage services such as deduplication and mirroring Database or financial functions Security algorithms AI/ML processing Overhead functions such as software-defined storage and virtualization They are particularly well-suited to large clouds, which want to offload overhead activities so they can dedicate processors to chargeable tasks. The high volumes involved here allow manufacturers to provide custom solutions combining circuitry for a cloud’s specific needs with a standard NIC design. An obvious problem is keeping tasks executing on SmartNICs from interfering with each other, an essential feature for cloud applications.
About the Organizer/Moderator:
Satish Kikkeri is Sr Director Product Management at Fungible, a leading maker of data processor units (DPUs). He works on product strategy, definition, roll-out, and go-to-market. He has broad experience across SDN, NFV, NVMe and NVMe-oF, SD-WAN, virtualization, and containers. Before joining Fungible, he was Head of Product Marketing and Product Management for Marvell’s Ethernet Server Adapter Group, where he was responsible for the industry-leading LiquidIO SmartNIC product. He has also worked at Symmetricom and Huawei. He has spoken at conferences and tradeshows worldwide including Gartner Summit, IDC Conference, Cloud Computing World Forum, and Interop. He earned an MBA from the University of Southern California and an MS in computer science from Utah State University.

Coming soon..

Wednesday, April 27th
2:00 PM-
C-101: Panel on Best Way to Program SmartNICs Today (Panels Track)
Moderator: David McIntyre, Director Product Planning, Samsung Electronics

Panel Members:
Panelist: Donglai Dai, Chief Engineer, X-ScaleSolutions

Panelist: Mario Baldi, Fellow, Pensando Systems

Panelist: Andrei Warkentin, ARM Enablement Architect, VMware

Panelist: Joe White, Fellow, Dell

Panelist: Trevor Caulder, Principal Developer Advocate, NVIDIA

Session Description:
Software development is a major issue for SmartNICs, since it often takes a long time and is very expensive. Furthermore, the number of units is not likely to be large enough to allow amortization to have much effect. Also many of the standard operating systems and development environments are available only for X86 processors, not the ARM or RISC-V cores most commonly used in SmartNICs. The addition of other computing elements such as GPUs, DPUs, and AI chips further complicates the process. Developers can counter such problems in various ways, such as using open-source software (for example, the P4 programming language) or commercial modules or IP. Software offers tremendous flexibility, but can cost a bundle even if the latest standard development methods are used.
About the Organizer/Moderator:
David McIntyre is Director Product Planning at Samsung Semiconductor, where he leads product planning and business enablement for computational storage. He focuses on data center cloud to edge acceleration solution in data analytics, security, and AI. He is also a member of the SNIA Computational Storage SIG and a program participant at the Persistent Memory Summit, Flash Memory Summit, and other forums. Before joining Samsung, he worked at Xilinx where he handled new data center initiatives including blockchain. He has also worked at Intel and Altera where he focused on storage, test, and measurement applications for FPGAs. He earned an MSEE from Ohio University and an MBA from San Jose State University.

Wednesday, April 27th
3:10 PM-
A-102: Standards (Architectures/Software/Tools Track)
Moderator: Claudio DeSanti, Distinguished Engineer, Dell

Paper Presenters:
Standardizing SmartNICs for COTS Horizontally-Integrated Solutions - Click for Proceedings:
Andrei Warkentin, ARM Enablement Architect, VMware

A Standard API for Accessing Compute Engines on a Network - Click for Proceedings:
Pavel Shamis, Sr Principal Research Engineer, Arm

Creating Software That 'Just Works' on SmartNICs - Click for Proceedings:
Dong Wei, Standards Architect, Arm

Session Description:
Customers generally want standardization of SmartNICs to avoid dependence on single vendors, allow for universal development tools and platforms, and create a wider and more useful ecosystem. SmartNICs are complex systems, so standards for them will require a lot of work. Standards must cover the basic datapath as well as hardware and software interfaces for applications to use. They must also provide guidelines for writing software that will work on a range of devices and will permit a variety of hardware and software structures, including the use of coprocessors such as DPUs, GPUs, and AI devices. Several standardization efforts are already underway, and a governing body may be needed to coordinate them.
About the Organizer/Moderator:
An experienced architect with a long history in the Internet industry, Claudio DeSanti is a Distinguished Engineer at Dell. He works on technology standardization and evangelization, Ethernet, storage area networks, and open interfaces. He was previously an Architect at Google and a Fellow at Cisco. He is the inventor of FCoE (Fibre Channel over Ethernet) and Chairman of the IEEE P802.3cs “Super-PON” task force. He has presented at many conferences, holds several patents, and is the recipient of four INCITS technical awards. He earned a PhD in computer engineering from Scuola Superiore Sant' Anna (Pisa, Italy).

Wednesday, April 27th
3:10 PM-
B-102: Storage/Security Applications (Edge/Data Center Applications Track)
Moderator: John Kim, Director Storage Marketing, NVIDIA

Paper Presenters:
Five Ways that SmartNICs and DPUs Enhance Cybersecurity - Click for Proceedings:
John Kim, Director Storage Marketing, NVIDIA

Session Description:
Storage applications include SAN, NAS, and RAID, as well as standard utilities such as deduplication, encryption/decryption, mirroring, and other functions. SmartNICs can offload tasks from central processors, thus avoiding bottlenecks in networked systems. They can also promote modularity, scalability, and flexibility. Much of the storage management overhead can move to the SmartNICs, thus greatly simplifying the implementation of upgrades, revisions, and new policies. SmartNICs can also be used to implement system-wide views, such as software-defined storage, object storage, or networked filesystems. Security applications include deep packet inspection, firewalls, and defenses against denial-of-service (DDoS) attacks. SmartNICs isolate the security functions for easy updating or replacement, keep threats well away from central facilities, and remove overhead functions so compute units can spend their time doing customer applications.
About the Organizer/Moderator:
John Kim is Director Storage Marketing for NVIDIA’s Networking Division. At NVIDIA, he builds technology solutions and partnerships, researches markets, defines product requirements, and evangelizes new solutions and products to sales, analysts, and customers. Before joining NVIDIA, he worked at Mellanox, EMC, and NetApp. He has been a blogger, a Webinar presenter, and a speaker at SNIA’s Storage Developer Conference. He has over 20 years experience in the storage industry. He earned a Bachelor’s degree from Harvard University.

Wednesday, April 27th
3:10 PM-
C-102: Panel on Next Great Breakthrough in SmartNICs (sponsored by Canonical) (Panels Track)
Session Sponsor: Canonical
Moderator: Endric Schubert, CTO, Missing Link Electronics

Panel Members:
Panelist: Derek Chickles, Director Machine Learning, Marvell

Panelist: Manoj Roge, HPC / Data Center Segment Lead, Synopsys

Panelist: Rob Davis, VP Storage, NVIDIA

Panelist: Ahmet Houssein, CEO, SiPanda

Panelist: Frode Nordahl, Sr Engineer, Canonical

Session Description:
Many important changes will surely occur in the emerging SmartNIC arena. They include the addition of standard slots for GPUs and DPUs, faster processors, more canned applications (perhaps available via an app store), more standards, and greater use of processors other than standard ARM cores. Other possible advances could include the integration of on-board optics, higher frequency versions of Ethernet, the use of persistent memory, and the use of higher-speed interfaces such as CXL.
About the Organizer/Moderator:
Endric Schubert is an experienced technologist and entrepreneur in electronic and semiconductor design. He is currently CTO at Missing Link Electronics, which specializes in FPGA-based acceleration for networking, communications, and storage applications. His background includes software engineering, FPGA technology, reconfigurable computing, and embedded systems design. He has extensive experience in FPGA-based design, ASIC development, IP creation, and software development. He has authored technical publications, holds several patents, and has given lectures on electronic system design. Endric earned an Electrical Engineering degree (Dipl.-Ing.) from University of Karlsruhe, Germany and a PhD in computer science from the University of Tubingen, Germany.

Wednesday, April 27th
4:20 PM-
A-103: Development Tools/Platforms (Architectures/Software/Tools Track)
Moderator: Jim Ballingall, Executive Director, Industry-Academia Partnership

Paper Presenters:
Choosing a Platform for FPGA-Based In-Network Compute Acceleration - Click for Proceedings:
Endric Schubert, CTO, Missing Link Electronics

Ulrich Langenbach, Director Engineering, Missing Link Electronics
Simplifying Infrastructure Offload and Management on SmartNICs - Click for Proceedings:
Kyle Mestery, Sr Principal Engineer, Intel

Developing Software for Data Center Infrastructure Applications - Click for Proceedings:
Deb Chatterjee, Network Acceleration Team Lead, Intel

Session Description:
There are many development platforms already available for SmartNICs. Manufacturers often supply one, and others are available from open-source projects or software vendors. Developers should pick a platform that supports many SmartNICs, is easy to use, and has a large ecosystem of tools and other support. An open-source platform is often a good first choice when developers are uncertain as to how to proceed. Many open-source tools and utilities are also available, including ones created in university environments.
About the Organizer/Moderator:
Jim Ballingall is the Executive Director of the Industry-Academia Partnership (IAP), an association dedicated to advancing cloud technologies to meet the demands of data centers and their customers. It focuses on both applications and infrastructure , bringing together industry and university partners on issues such as AI/ML, hardware acceleration, operating systems, networking, big data, security, storage, and data management. Before joining IAP, Jim was VP Global Marketing at GlobalFoundries, a leading worldwide semiconductor fab. He has over 25 years experience in the semiconductor industry. He earned a PhD in applied physics from Cornell University and a BS in engineering physics from UC Berkeley.

Wednesday, April 27th
4:20 PM-
B-103: High-Performance Computing (Edge/Data Center Applications Track)
Moderator: Addison Snell, CEO, Intersect360 Research

Paper Presenters:
A SmartNIC Developed for Scientific Applications
Yatish Kumar, R&D Architect, ESnet

Accelerating HPC Applications with SmartNICs - Click for Proceedings:
Donglai Dai, Chief Engineer, X-ScaleSolutions

Session Description:
High-performance computing is an obvious application for SmartNICs. HPC practitioners are always looking for more performance at relatively low cost. Offloading overhead functions to SmartNICs allow expensive compute units to spend their time doing useful work. Network protocol handling, message-passing, security, and utilities such as encryption/decryption, compression/decompression, and error handling are among the typical tasks often turned over to relatively inexpensive SmartNICs. Besides, new supercomputers don’t come along very often, so one needs to get all the performance possible from current hardware.
About the Organizer/Moderator:
Addison Snell is the CEO of Intersect360 Research and a veteran of the high performance computing (HPC) industry. He has established Intersect360 Research as a premier source of market information, analysis, and consulting. He was named one of 2010's "People to Watch" by HPCwire. He is a regular participant at both Supercomputing and the ISC High-Performance conferences as a speaker, panelist, and chairperson. Before co-founding Intersect360, Addison was an HPC industry analyst for IDC, where he was well-known among industry stakeholders. Before joining IDC, he was a marketing leader and spokesperson for SGI's supercomputing products and strategy. Addison holds a master's degree from the Kellogg School of Management at Northwestern University and a bachelor's degree from the University of Pennsylvania.

Wednesday, April 27th
4:20 PM-
C-103: Panel on Optimizing SmartNIC Applications (sponsored by Napatech) (Panels Track)
Moderator: Leonid Grossman, Director, NVIDIA

Panel Members:
Panelist: Vikram Singh, Sr Product Line Manager, Juniper Networks

Panelist: Rong Pan, Fellow, Intel

Panelist: Jarrod J.S. Siket, CMO, Napatech

Panelist: Prasun Kapoor, Sr Director of Software Engineering, Marvell

Panelist: Nabil Damouny, Principal, Autonomous Edge

Session Description:
The usual issue is to get applications to run faster. One common problem is a slow network stack, so check around to see if yours is the latest version or team members or associates have found others to be more efficient. Other common approaches include replacing the processor with a faster model – some SmartNICs have chips that are way behind the state-of-the-art. Still other alternatives are replacing or upgrading the message passing mechanism that starts up the SmartNIC and moves its results – everything may be delayed if messages are not being generated or recognized efficiently. Some NICs even have internal features that offload or speed up message processing. Other system software may also run much faster if it executes at the network level rather than the host level. There are even tools available that can predict how large a performance gain you can expect from offloading.
About the Organizer/Moderator:
Leonid Grossman is Director of Cloud Network Engineering at NVIDIA, where he works on a private cloud that involves large numbers of SmartNICs. Before joining NVIDIA, he was Director Software Development at Oracle where he delivered the networking roadmap for Oracle Solaris and led its integration with the public cloud. He also represented Oracle in the Open Networking Foundation and the OpenDaylight SDN Project team. He previously worked on 10GbE networking software at Neterion, where he was a co-founder and VP Software Engineering. He earned a Master’s degree in computer science from the Moscow Institute of Physics and Technology.