Tuesday, April 26th
Tuesday, April 26th
1:00 PM-
Pre-Conference Tutorial A: SmartNIC Basics (Pre-Conference Tutorials Track)
Moderator: Scott Schweitzer, Sr Manager Product Planning, Achronix

Speaker(s):
Presenter: Motti Beck, Sr Director, NVIDIA

Presenter: Ash Bhalgat, Sr Director, NVIDIA

Session Description:
SmartNICs are an important new technology that brings the advantages of edge and distributed technology to today’s networks. They have their own on-board compute elements, which can perform tasks ranging from protocol offload through a variety of systems and applications tasks. They reduce the burden on central processors, allowing them to focus on their primary functions rather than on overhead or work better left to specialty devices. The result is faster, more scalable, and more modular networks better-suited to today’s clouds and data centers. SmartNICs are now available with a variety of architectures. The major difference is in the processing elements. ASIC and FPGA-based devices perform tasks at hardware speeds, but have little flexibility. Processor-based ones are slower but can do almost any task as long as software is available or can be developed. Obviously, software development becomes a major issue. The future of SmartNICs is bright. Most now offload network protocols, thus reducing the overhead that the central processor must handle. Other use cases include storage interfaces, data processing operations such as encryption or compression, media management, AI/ML, virtualization, or security.
About the Organizer/Moderator:
Scott Schweitzer is Sr Manager Product Planning at Achronix Semiconductor, where he helps define SmartNIC and data center accelerator products for FPGAs. He was previously a Technology Evangelist at Xilinx, where he focused on acceleration and helped customers and partners recognize new opportunities and define new innovative solutions. He has also produced the popular blogs TechnologyEvangelist.com and 10GbE.net, which received thousands of monthly page views, and written a series of three articles on SmartNICs for Electronic Design magazine. Before joining Xilinx, Scott worked at SolarFlare Communications, Myricom, NEC Solutions America, and IBM. He earned an MS in Computer Science from NYU’s Tandon School of Engineering.

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Tuesday, April 26th
1:00 PM-
Pre-Conference Tutorial B: Introduction to the P4 Programming Language (Pre-Conference Tutorials Track)
Moderator: Mario Baldi, Fellow, Pensando Systems

Speaker(s):
Presenter: Alex Seibulescu, Compiler Development, Pensando Systems

Presenter: Carmelo Cascone, Sr Staff Engingeer, Intel

Presenter: Deb Chatterjee, Network Acceleration Team Lead, Intel

Presenter: Chris Neely, Research Engineer, AMD

Presenter: Mario Baldi, Fellow, Pensando Systems

Presenter: Steven Zagorianakos, Chief Silicon Architect, Netronome

Session Description:
P4 is a programming language for specifying how network devices such as switches, routers, and NICs process packets. Vendors have used it as the programming language of choice for many products, such as the Cisco Silicon One chipsets, the Barefoot Tofino switches, the Pensando Distributed Services Cards, the AMD SN1000 SmartNIC, and the Aruba CX 10000 smart switch. It is particularly useful for today’s applications that employ software-defined networking (SDN). Using P4 makes network devices easier to program, debug, document, maintain, and update. The main ideas behind P4 are: * Close relationship with typical packet processing tasks. P4 programs specify how packet headers are parsed and what actions are taken based on field values. * Protocol independence: Network devices are not tied to specific protocols. * Target independence: Programmers can describe packet processing for any underlying hardware. * Reconfigurability in the field: Programmers can change the way switches process packets after deployment. The P4 ecosystem includes an extensive range of products, projects, and services. The P4 website (p4.org) is a great source to learn about P4 and join the community. P4’s current tasks include the definition of a Portable NIC Architecture (PNA). Special Feature: Attendees will have opportunities to write P4 code and corresponding control plane functions.
About the Organizer/Moderator:
Mario Baldi is a Fellow at Pensando Systems, where he is in charge of product management for APIs, software development environments, and the third generation system-on-chip. He also participates in the Architecture Workgroup of the P4 community. He was previously Director of Technology at Cisco, where he helped develop the operating system for Nexus switches. He earned a PhD in computer engineering from the Politecnico di Torino (Italy). He has published articles and given presentations on the P4 language and SmartNIC applications.

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Speaker Bio: Chris Neely is a Research Engineer at AMD, where he performs packet processing and SmartNIC-related research. He was previously the Technical Lead for AMD-Xilinx's SDNet packet processing product, which was the first commercial application to support P4_16. He has published eight articles with an emphasis on reconfigurable computing and programmable logic. He holds five patents. His areas of interest include SmartNICs, networking, FPGAs, and embedded systems. He earned a PhD in Computer Engineering from Santa Clara University.

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Tuesday, April 26th
3:15 PM-
Refreshment Break (Pre-Conference Tutorials Track)
Paper Presenters:
Session Description:
Coming soon..
About the Organizer/Moderator:
Tuesday, April 26th
5:00 PM-
Chat with the Experts (Beer/Pizza Expert Table Leaders Event) (Pre-Conference Tutorials Track)
Moderator: Jon Stroud, System Architect, Keysight Technologies

Paper Presenters:
ASIC-Based Devices Table
Rob Davis, VP Storage, NVIDIA

Security
Brent Cook, Security Director, Stealth Startup

Data Center Applications
Venkat Pullela, Chief of Technology Networking, Keysight Technologies

DPUs
Frode Nordahl, Sr Engineer, Canonical

Networking Applications
Yatish Kumar, R&D Architect, ESnet

Architectures Table
Andrei Warkentin, ARM Enablement Architect, VMware

Testing
Chris Sommers, Software Architect, Keysight Technologies

Application Acceleration Table
David McIntyre, Director Product Planning, Samsung Electronics

FPGA-Based Devices
Endric Schubert, CTO, Missing Link Electronics

Future SmartNIC Features
Scott Schweitzer, Sr Manager Product Planning, Achronix

Session Description:
Coming soon..
About the Organizer/Moderator:
Jonathan Stroud is a Senior Systems Architect at Keysight Technologies, where he develops innovative network test and visibility solutions. Before joining Keysight, Jon worked at Breaking Point Systems and Ixia where he focused on RTL based SmartNIC offloads and network processor software to help revolutionize layer 4-7 network application and security testing. He holds three patents in network flow analysis. He studied computer and electrical engineering at North Carolina State University.