Keynote 5: Cadence

Chiplets for Everyone

About the Speaker: David Glasco has been Cadence's Vice President of the Compute Solutions Group since 2021. In this role, he oversees the design and development of hardware and software for Cadence?s extensive soft IP portfolio which includes the Neo NPU, NeuroWeave AI Compiler, Memory Controllers, Interface Controllers, System IP, NoC, and Chiplet implementation groups. Before joining Cadence, David held key positions focused on SoC design efforts, including the Tesla FSD SoC, Amazon Kuiper Modem SoC, and Newisys Opteron CC-NUMA SoC. He spent twelve years at NVIDIA, leading various teams responsible for GPU memory system architecture, ISP design, and initiatives within NVIDIA Research. Additionally, he has served on the Technical Advisory Boards of NetSpeed and Terradepth.David earned his PhD in electrical engineering from Stanford University. He is an accomplished inventor with over 100 patents and numerous publications.

Abstract: The semiconductor industry is transitioning from traditional monolithic system-on-chip (SoC) architectures to modular, multi-die designs to tackle rising transistor costs, product configurability, scaling challenges, and fabrication complexities. The vision is for off-the-shelf, plug-and-play chiplets to enable scalable product development at lower cost, and faster than ever before. Physical AI, in particular, demands a unique combination of sensors, processing power, and I/O. Chiplets provide the modularity to integrate these technologies seamlessly, delivering high-performance compute directly at the edge, where real-time action occurs. Attendees will learn about the current state of multi-die design, the evolving requirements for chiplets across data center, edge and Physical AI applications, and the critical role of standardization and robust ecosystems in driving adoption. They will see how chiplets are redefining semiconductor design, enabling scalable innovation, and shaping the future of edge and Physical AI.

Special Presentation 3: SNIA

SNIA: A Leader in Storage for the Age of AI

About the Speaker: Scott Shadley is a 29 year Industry Veteran with experience in all aspects of Semiconductor Manufacturing, Design, and Market Growth. He has served as a SNIA Executive Board member for 3 terms, and leads the communications strategy for SNIA. His current role as Director of Leadership Narrative and Evangelist for Solidigm is focused on driving innovation and ensuring market alignment across all aspects of the storage industry. Having “Pieced Together” many winning strategies over his career, Scott is going to share the value of SNIA to the Chiplet market and what is in store for the future.

Abstract: The age of AI is upon us, and SNIA plans to play an important role in it. We will provide standards, best practices, and joint efforts to deal with storage for AI, distributed storage systems, high-speed storage interfaces, and storage networks. We also plan to take a lead position in storage chiplets, storage processors, and storage software. We expect a huge new demand for extremely large, high-speed, and low-latency storage systems, and we plan to continue our efforts to make such systems fast, scalable, cost-effective, and easy to use.

Keynote 6: Arm

Arm’s Open Chiplet Ecosystem for the Converged AI Datacenter

About the Speaker: Imran Yusuf is an accomplished executive with extensive experience in hardware ecosystems, strategic alliances, and business development. Currently serving as Director of Hardware Ecosystem at Arm since April 2020, Imran previously held key roles at Enea AB, including Vice President of Strategic Alliances and Business Development, where efforts significantly enhanced sales and brand visibility in the universal CPE market. Prior experience at Enea's Qosmos Division and Wind River focused on partner strategies and ecosystem development, while positions at Intel encompassed business development, technical marketing, and project management, contributing to substantial revenue growth and innovative product solutions. Imran holds multiple degrees from Georgia Institute of Technology, including a Master of Science in Mechanical Engineering, a Master of Science in Aerospace Engineering, and a Bachelor of Aerospace Engineering.

Abstract: AI is reshaping global infrastructure, and the converged AI datacenter is driving unprecedented diversity in silicon requirements. These environments bring together CPUs, AI accelerators, memory and cache expansion dies, high bandwidth I O, networking, security, storage, and data movement engines to support a mix of AI, cloud, and traditional workloads. Monolithic SoCs cannot evolve quickly or economically enough to meet these needs, making chiplet based architectures essential for enabling reuse, specialization, and modular growth. In this keynote, we will highlight cloud providers and AI innovators already using chiplet based integration to build more flexible and efficient infrastructure, demonstrating how an open chiplet ecosystem can scale innovation across all types of silicon and create a sustainable foundation for the next decade of AI and cloud growth.

Special Presentation 4: IEEE

IEEE and the Future of Chiplets

About the Speaker: Tom Coughlin, President, Coughlin Associates is a digital storage analyst and business/ technology consultant. He has over 40 years in the data storage industry with engineering and senior management positions. Coughlin Associates consults, publishes books and market and technology reports and puts on digital storage and memory-oriented events. He is a regular contributor for forbes.com and M&E organization websites. He is an IEEE Fellow, 2025 IEEE Past President, Past-President IEEE-USA, Past Director IEEE Region 6 and Past Chair Santa Clara Valley IEEE Section, and is also active with SNIA and SMPTE. For more information on Tom Coughlin go to www.tomcoughlin.com

Keynote 7: Open Compute Project

Open Ecosystems for the Next Wave of AI: Inference

About the Speaker: Anu Ramamurthy is the co-lead on the Open Chiplet Economy sub-group of the Open Compute Proejct and an Associate Fellow, Design at Microchip Technology. She has 25 years' experience in the semiconductor industry and her current interests are advanced packaging and heterogeneous integration. This includes all aspects of the ecosystem, starting with the technology, packaging, architecture, test, system integration and cost modeling of such designs. She is also very interested in mentoring women in engineering, has been part of the TechWomen program run by the U.S State department and also actively involved in the mentoring programs at Microchip.

About the Speaker: Cliff Grossner is Chief Innovation Officer at OCP where he leads its market intelligence and drives new programs. His major efforts include guiding inventors in developing early-stage company ideas, setting strategic direction and building awareness of OCP, and establishing new alliances and activities. Before joining OCP, he headed the Cloud and Data Research Practice at Informa Tech, where he worked on cloud services, data center compute and networking, and data center infrastructure. He previously held senior positions at Alcatel-Lucent, Bell Labs, and Nortel. He earned his PhD at McGill University (Canada) and holds over 10 patents in networking and telecommunications.

Abstract: The next wave of AI is focused on optimizing AI inference at points-of-presence near the user, and in regional and hyperscale cloud data centers. Making this happen quickly and cheaply, requires standardized chips that fit everywhere for silicon diversity. The key to quickly developing low-cost ecosystems will be standards enabling an interoperable chiplet-based open ecosystem. Allowing a combination of low-cost chips that meet the needs of particular environments, applications, and pave the way to success. For 2026, this is a main focus for Open Compute Project’s (OCP) Open Compute Economy Project.

Keynote 8: Marvell

Optimizing Cutting-Edge XPUs with Chiplets

About the Speaker: Jim Rogers is Senior Vice President, Custom Cloud Solutions at Marvell, where he is responsible for driving the company's custom silicon strategy and execution for leading hyperscalers. Jim joined Marvell in 2019 as Vice President, Commercial ASIC Business and has more than 15 years of experience managing leading-edge custom businesses. In 2010, following a successful startup venture within IBM, Jim led IBM?s leading-edge ASIC Business Unit. In 2015, he oversaw the transition of this unit to GlobalFoundries and, later, in 2019, its integration into Marvell through the Avera acquisition. At GlobalFoundries, Jim spearheaded the company's expansion into the data center market, moving beyond its traditional communications focus. Earlier in his career, he participated in IBM's executive development program and held several leadership roles at IBM and AMI Semiconductor. Jim earned both his B.S. in Electrical Engineering and M.S. in Electrical Engineering and Materials Science from the University of Vermont.

Abstract: Power is the new currency of the datacenter. AI growth is constrained by power, not performance, as the AI build-out is outpacing the ability to generate electricity. This presentation will review the evolution of new memory and connectivity technologies in the form of chiplets – including 3D packaging, >30Tbps/mm D2D interconnect, custom SRAM, custom HBM, integrated power management and integrated optics – that will dramatically reduce the power consumption and increase the performance of the next generation of XPUs.