Introduction to Chiplet Summit

Introduction to 2026 Summit

About the Speaker: Chuck Sobey is the General Chair of Chiplet Summit. He leads the Organizing Committees and identifies key trends, sessions, and speakers. Chuck is also Chief Scientist of ChannelScience, where he secured ~$3M in seed funding to develop a multi-format magnetic tape reader to access rare and deteriorating data sets. These data sets will be used for domain-specific training of AI/ML models, such as for monitoring data for nuclear nonproliferation efforts globally. Chuck earned an MS in electrical and computer engineering from University of California, Santa Barbara (UCSB), a BS from Carnegie Mellon University, and holds 8+ US patents.

Abstract: The 4th annual Chiplet Summit will be the largest yet by far – reflecting the greater importance of chiplets to the semiconductor industry. After a quick review of the opening tutorials, SuperPanel, and Chat with the Experts, an overview of the conference provides a roadmap for navigating the sessions and panels. Insider tips will help attendees get the most from their time at Chiplet Summit. Key questions for answering during the event will come next, and a glimpse at what is in store for Chiplet Summit 2027 will follow! This brief introduction and welcome will precede our popular plenary session. In it, top experts cover the current state of chiplet technology and chiplet markets. After that come our visionary keynotes, followed by the opening of the exhibits.

Keynote 1: Synopsys

Designing the Future Today: AI-Driven Multi-Die Design

About the Speaker: Abhijeet Chakraborty is VP Engineering at Synopsys, where he is responsible for the development of multi-die and 3D heterogeneous integration technologies and solutions. He led the development of Design Compiler-NXT, the leading synthesis product in the industry. He has held R&D leadership roles at highly regarded startups including Magma Design Automation. Abhijeet holds several patents, is on technical advisory boards, has given keynotes and been a panelist in several conferences including DAC and ECTC. He is a graduate of the University of Texas at Austin and Indian Institute of Technology, Bombay.

Abstract: As multi-die designs grow in complexity, artificial intelligence (AI) is emerging as a critical enabler for optimizing design, integration, and verification processes. This keynote will explore how AI is revolutionizing multi-die design through advanced automation. Attendees will get a visionary perspective on the future of intelligent, automated multi-die design.

Special Presentation 1: Fraunhofer

Chiplets for Automotive, Industrial, and Aerospace Applications

About the Speaker: Andy Heinig is the Technical Leader of the Advanced Packaging Workgroup at the Fraunhofer Institute IIS/EAS, where he works on assembly design kits and design flows for packaging. He has started several major German and European research projects in design and design automation for advanced packaging. He has also worked extensively in several standardization groups such as SI2. Heinig has 55 publications, including presentations at important conferences such as the Electronic Components Technology Conference (ECTC), Electronic Packaging Technology Conference, and the IEEE Conference on Electronics, Circuits, and Systems (ICECS), and in journals such as the IEEE Transactions on Components, Packaging, and Manufacturing Technology. He earned a Diploma degree in information technology from the Technical University of Cottbus (Germany).

Keynote 2: Alphawave Semi

Engineering the Chiplet Era: Connectivity the Foundation of System-Level Design

About the Speaker: Letizia Giuliano is Vice President of Product Marketing and Management at Alphawave Semi, specializing in high-speed connectivity and chiplet design. With over 20 years of experience in semiconductor IP and SoC, she has held key roles at Alphawave Semi, Intel, and STMicroelectronics, driving innovation in ASIC design, technical marketing, and industry standards development. At Alphawave Semi, Letizia and her team manage the IP portfolio, driving innovation to enhance high-speed connectivity and chiplet technology. Committed to advancing an open-chiplet ecosystem, she champions multi-company chiplet integration, accelerating the development of next-generation complex systems in package. She regularly speaks at industry conferences such as the Chiplet Summit, DAC, and EETimes? Chiplet Seminar, sharing insights on chiplet advancements and standards. Letizia holds a Master of Science in Electrical Engineering from Politecnico di Milano and currently resides in Portland, Oregon.

Abstract: As chiplets move from early adoption to mainstream deployment, the focus of innovation is shifting from individual dies to system-level architecture. As we gather at the fourth year of the Chiplet Summit, it is clear that high-performance, power-efficient connectivity is the critical enabler that determines scalability, interoperability, and product viability.

Special Presentation 2: Silicon Catalyst

Catalyzing Chiplet Startups

About the Speaker: Nick Kepler is COO at Silicon Catalyst, where he works with partners and early-stage and incubator companies. He has previously been VP Corporate Program Management at GlobalFoundries and VP Technology Development at AMD. He has also been VP Products at SuVolta, a startup developing semiconductor technology IP. He earned an MSEE from the University of California at Berkeley and has over 30 years experience in the semiconductor industry.

Abstract: Nick Kepler will explore the vital role startups play in advancing semiconductor innovation, highlighting how strong ecosystems and experienced leadership help turn breakthrough ideas into market-ready solutions. By framing chiplets not merely as a technical innovation but as a business enabler, the presentation will reinforce a core theme of the summit: success in the chiplet era depends as much on ecosystem coordination as on engineering excellence.

Keynote 3: Siemens

Redefine 3D IC Performance for AI -- with AI

About the Speaker: Juan C. Rey returned to the Calibre Segment and was appointed as Sr. Vice President, Segment Leader/General Manager for Siemens EDA in April of 2025. Prior to his appointment as GM, Juan led the Central Engineering Solutions Team as part of a government program focused on 3D flows. He Transitioned to Central Engineering Solutions Team after serving as Vice President of Government Programs for Siemens EDA where he was responsible for defining technical programs to support government initiatives since 2023. Prior to his work with Government Programs, Juan held the roll of Vice President of Calibre Engineering. He joined Mentor Graphics in 2001 as Senior Engineering Director for Mentor?s industry-leading Calibre product line, directing all development activities for Calibre products, a role he performed until December 2021. Prior to his time at Mentor Graphics, Juan was Vice President of Engineering at Exend Corporation, managing all software development and quality activities. He joined Extend after serving as Engineering Director of Physical Verification at Cadence Design Systems. Earlier positions include Manager/Developer for Process Modeling and Parasitic Extraction at Technology Modeling Associates, Visiting Scholar/Science and Engineering Associate at Stanford University, Senior Research Engineer at INVAP, Argentina, and Associate Professor at Universidad Nacional del Comahue, Argentina. Juan holds a degree in Nuclear Engineering from Universidad Nacional de Cuyo, Argentina. The author or co-author of numerous papers and conference presentations, he serves on the Executive Technology Advisory Board of Semiconductor Research Corporation (SRC) and the UCLA Center for Domain-Specific Computing.

Abstract: AI is pushing the limits of semiconductor performance. Today’s AI accelerators already deliver 20, 50 even 100 petaflops of compute — and 150 is not far away. Achieving that future demands a fundamental shift from 2D design to 3D heterogeneous integration to realize superior system-level PPA. However, traditional 2D design flows can no longer keep pace with the scale and cross-domain complexity of 3D ICs. Engineers now grapple with millions of micro-bumps and interconnects, intricate multiphysics interactions from dies to systems and massive design data across teams. The question is no longer “if” — but “how” — the industry can unlock the full potential of 3D ICs for AI, with AI. In this keynote, Juan Rey, General Manager at Siemens EDA, will examine the top barriers to 3D IC performance and reliability and outline the industry’s path toward a more open, holistic, AI-driven design flow. He will introduce five essential design strategies spanning from early system planning through multi-die sign-off, that help design teams accelerate design convergence, enhance predictability and reduce design costs. The audience will also see real-world examples of how design teams use Siemens’ unified AI-driven design flows and digital twin technologies to deliver reliable 3D IC systems at AI scale.

Keynote 4: UCIe Consortium

Enabling an Open Chiplet Ecosystem at the Package Level

About the Speaker: Debendra Das Sharma is a member of the Board of Directors for the PCI Special Interest Group (PCI-SIG) and a lead contributor to PCIe specifications since its inception. He is a co-inventor and founding member of the CXL consortium, co-leads the CXL Board Technical Task Force, and is a leading contributor to CXL specifications. He co- invented the chiplet interconnect standard UCIe and is the chair of the UCIe consortium. Dr. Das Sharma has a bachelor’s in technology (with honors) degree in Computer Science and Engineering from the Indian Institute of Technology, Kharagpur and a Ph.D. in Computer Engineering from the University of Massachusetts, Amherst.​ He holds 180+ US patents and 450+ patents world-wide. He is a frequent keynote speaker, plenary speaker, distinguished lecturer, invited speaker, and panelist at the IEEE Hot Interconnects, IEEE Cool Chips, IEEE 3DIC, SNIA SDC, PCI-SIG Developers Conference, CXL consortium, Open Server Summit, Open Fabrics Alliance, Flash Memory Summit, Intel Innovation, and Universities (CMU, Texas A&M, Georgia Tech, UIUC, UC Irvine). He has been awarded the Distinguished Alumnus Award from Indian Institute of Technology, Kharagpur in 2019, the IEEE Region 6 Outstanding Engineer Award in 2021, the first PCI-SIG Lifetime Contribution Award in 2022, and the IEEE Circuits and Systems Industrial Pioneer Award in 2022.