Keynote 5: Cadence

About the Speaker: Boyd Phelps is Sr VP/GM of Cadence's Silicon Solutions Group (SSG) where he manages the IP and Silicon Solutions portfolio, investments, and roadmaps. He was previously a Corporate VP at Intel, where he led the design teams for client SoCs and X86 CPUs. He holds patents and has been a prominent speaker at industry conferences including ISSCC and HotChips. He earned a BSEE at Brigham Young University and graduated from the Stanford Executive Accelerator program.

Abstract: The semiconductor sector is undergoing a paradigm shift from traditional monolithic System-on-Chip (SoC) architectures to a modular chiplet-based design framework aimed at mitigating the complexities associated with design scale, yield optimization, and escalating fabrication costs. This transition is primarily driven by economic factors, including the increasing cost per transistor and the diminishing returns of Moore's Law. The changeover requires advanced and comprehensive solutions that cater to a wide range of system requirements and enable efficient chip design through advanced tools and IP. To fully harness the benefits of chiplets, the industry must effectively address technical challenges of dual foundry integration, cache coherency protocols, power management strategies, and the development of a unified design architecture. Integrating these critical components is essential to accelerate the adoption of chiplets, utilizing the full spectrum of the design ecosystem to capitalize on this innovative design methodology.

Special Presentation 3: SNIA

About the Speaker: Scott Shadley is a 29 year Industry Veteran with experience in all aspects of Semiconductor Manufacturing, Design, and Market Growth. He has served as a SNIA Executive Board member for 3 terms, and leads the communications strategy for SNIA. His current role as Director of Leadership Narrative and Evangelist for Solidigm is focused on driving innovation and ensuring market alignment across all aspects of the storage industry. Having “Pieced Together” many winning strategies over his career, Scott is going to share the value of SNIA to the Chiplet market and what is in store for the future.

Abstract: The age of AI is upon us, and SNIA plans to play an important role in it. We will provide standards, best practices, and joint efforts to deal with storage for AI, distributed storage systems, high-speed storage interfaces, and storage networks. We also plan to take a lead position in storage chiplets, storage processors, and storage software. We expect a huge new demand for extremely large, high-speed, and low-latency storage systems, and we plan to continue our efforts to make such systems fast, scalable, cost-effective, and easy to use.

Keynote 6: Keysight Technologies

About the Speaker: Nilesh Kamdar is General Manager Design and Verification at Keysight Technologies, where he manages RF and microwave device modeling, system EDA, power electronics, and interoperability. He has previous experience in software business and operations, circuit simulation, and applications engineering. He has presented at events, including the International Microwave Symposium (IMS), and is often interviewed in the trade and technical press. He earned an MSEE at Utah State University

Abstract: The development process for chiplet-based designs is considerably more complex than for monolithic ones. In the first place, designers must select a chiplet interconnect based on speed, features, and ecosystem. They then must work with the foundry to choose an advanced package and understand how heterogeneous integration will proceed. Test and design workflows must be integrated to ensure that only known good dies proceed to the later stages. The interconnect (such as UCIe) requires special attention since the common options are all new, so designers should acquire proven IP to speed up the process. Proven IP may also help by providing components such as processors, memory, I/O, and power and clock distribution. Designers should plan to use a commercially proven data management system to track all the IP going into the system. An example describes a complete chiplet workflow for an application aimed at the 5G/6G and optical domains and utilizing millimeter-wave technologies.

Keynote 7: Open Compute Project

About the Speaker: Anu Ramamurthy is an Associate Technical Fellow at Microchip Technology, where she works on heterogeneous integration and advanced packaging. She also has expertise in physical design and procurement management of 3rd party IP. Before joining Microchip, she worked at Microsemi and Vitesse Semiconductor as a design engineer and engineering manager. She earned an MS in semiconductor devices from North Carolina State University. She has been an organizer, presenter, and Organizing Committee member for Chiplet Summit.

About the Speaker: Cliff Grossner is Chief Innovation Officer at OCP where he leads its market intelligence and drives new programs. His major efforts include guiding inventors in developing early-stage company ideas, setting strategic direction and building awareness of OCP, and establishing new alliances and activities. Before joining OCP, he headed the Cloud and Data Research Practice at Informa Tech, where he worked on cloud services, data center compute and networking, and data center infrastructure. He previously held senior positions at Alcatel-Lucent, Bell Labs, and Nortel. He earned his PhD at McGill University (Canada) and holds over 10 patents in networking and telecommunications.

Abstract: Chiplets have rapidly become the efficient, cost-effective way to develop chips at leading-edge nodes and are being used successfully at almost all major semiconductor companies. OCP is working to provide an open environment where designers simply drop known-good third-party sourced chiplets into their designs. This requires a major change in the silicon supply chain and the development of an open marketplace. That marketplace must make available a catalog of standalone chiplets, new standards, tools and best practices. Although incorporating third-party known-good dies into a chip design is not yet straightforward, ongoing efforts at OCP's Open Chiplet Economy Project are paving the way for the future.