| Wednesday, January 22nd |
|  Charles SobeyGeneral ChairChiplet Summit
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| | Chairman WelcomeWednesday, January 22nd - 8:45 - 9:00 AM | Abstract: The 3rd annual Chiplet Summit reflects the rapid growth of chiplets, driven by AI acceleration and increasing options in the chiplet marketplace. Get the most out of your time at CS25 by learning about new event features such as the Packaging track, Chiplet marketplace, and Birds of a Feather (BoF) sessions. Ways to see the latest developments from leading chiplet companies and organizations will be highlighted. Learn about the tools to help you efficiently personalize your schedule with the tracks and sessions that will help you at your job and grow your network.
About Chiplet Summit: Chiplet Summit is the annual conference and trade show where the entire chiplet ecosystem meets! Technology leaders across all disciplines share solutions that advance chiplet design. Industry leaders set the direction to achieve interoperability in the growing chiplet marketplace. Experts showcase breakthroughs in AI, servers, domain-specific accelerators, telecom, IoT, and emerging applications
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|  Abhijeet ChakrabortyVP EngineeringSynopsys
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| | Accelerating AI Chip Development with 3D Multi-Die DesignsWednesday, January 22nd - 10:10 - 10:40 AM | About the Speaker: Abhijeet Chakraborty is VP Engineering at Synopsys, where he is responsible for development of Multi-Die solutions, and driving 3D heterogeneous integration in government programs. He led the development of Design Compiler-NXT, the leading synthesis product in the industry. He has held R&D leadership roles at highly regarded startups including Magma Design Automation. Abhijeet holds several patents, is on technical advisory boards, has given keynotes and been a panelist in several conferences including DAC and ECTC. He is a graduate of the University of Texas at Austin and Indian Institute of Technology, Bombay.
Abstract: Wide adoption of AI has led to strong demand for higher compute performance. Chiplet-based multi-die designs can answer the call using high-bandwidth communications, 3D-enabled IP, and methods for achieving seamless continuity from 2D to 3D. Leading-edge products show that a combination of all the approaches is the key to bringing multi-die designs into production.
About Synopsys: Synopsys (Nasdaq: SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. Learn more at www.synopsys.com.
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|  Brian ReaMarketing WorkGroup ChairUCIe Consortium
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| | Enabling an Open Chiplet Ecosystem at the Package LevelWednesday, January 22nd - 10:40 - 10:50 PM | About the Speaker: Brian Rea is a senior technologist in the industry initiative and technology enabling team at Intel and is the Marketing Working Group Co-Chair for the UCIe Consortium. Brian has held engineering, marketing, and strategic planning roles bringing products with new technologies to market including USB, Gigabit Ethernet, PCIe, and CXL. His passion is working with customers and partners to enable ecosystem innovations in silicon, hardware, and software. Brian holds an MBA from the University of Washington and a BSEE from the University of Texas at Austin.
About UCIe Consortium: The UCIe Consortium is an industry consortium dedicated to advancing UCIe™ (Universal Chiplet Interconnect Express™) technology, an open industry standard that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. UCIe Consortium is led by key industry leaders Advanced Semiconductor Engineering, Inc. (ASE), Alibaba, AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, NVIDIA, Qualcomm Incorporated, Samsung Electronics, and Taiwan Semiconductor Manufacturing Company.
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|  Tony Chan CarusoneCTOAlphawave Semi
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| | Scaling Connectivity for Chiplet-Based AI SystemsWednesday, January 22nd - 10:50 - 11:20 AM | About the Speaker: Tony Chan Carusone is CTO at Alphawave Semi, where he focuses on developing IP for communicating and processing information. He is also a professor of electrical engineering at the University of Toronto (Canada). He has over 100 published articles, including 11 award-winning best papers, and holds 7 patents. He has presented at many major conferences including ISSCC and CICC. He co-authored classic textbooks on “Analog Integrated Circuit Design” and “Microelectronic Circuits”. He earned a PhD in electrical engineering from the University of Toronto.
Abstract: Chiplets are paving the way for the next generation of AI systems. They are the key to scaling AI connectivity and compute. Immediate applications include scale-up, where chiplets enable more processing power within a system, and scale-out, where multiple chiplet-based systems work together. Advanced switches leverage chiplets to enhance data transfer rates and reduce latency. Meanwhile, optical connectivity, facilitated by chiplets, offers high-speed data transmission with lower power consumption, crucial for handling the massive data loads in AI applications.
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|  Nick KeplerCOOSilicon Catalyst
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| | Accelerating Chiplet StartupsWednesday, January 22nd - 11:20 - 11:30 AM | About the Speaker: Nick Kepler is COO at Silicon Catalyst, where he works with partners and early-stage and incubator companies. He has previously been VP Corporate Program Management at GlobalFoundries and VP Technology Development at AMD. He has also been VP Products at SuVolta, a startup developing semiconductor technology IP. He earned an MSEE from the University of California at Berkeley and has over 30 years experience in the semiconductor industry.
About Silicon Catalyst: Silicon Catalyst is the world’s only incubator focused exclusively on accelerating semiconductor solutions, built on a comprehensive coalition of in-kind and strategic partners to dramatically reduce the cost and complexity of development. More than 800 startup companies worldwide have engaged with Silicon Catalyst and the company has admitted 90 exciting companies. With a world-class network of mentors to advise startups, Silicon Catalyst is helping new semiconductor companies address the challenges in moving from idea to realization. The incubator/accelerator supplies startups with access to design tools, silicon devices, networking, and a path to funding, banking and marketing acumen to successfully launch and grow their companies’ novel technology solutions. Over the past seven plus years, the Silicon Catalyst model has proven to dramatically accelerate a startup’s trajectory while at the same time de-risking the equation for investors. Silicon Catalyst has been named the Semiconductor Review’s 2021 Top-10 Solutions Company award winner.
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|  Eddie RamirezVP Marketing - Infrastructure Business Unit,Arm
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| | Meeting the Challenge of Diverse AI Workloads with ChipletsWednesday, January 22nd - 11:30 - 12:00 PM | About the Speaker: Eddie Ramirez is VP Marketing/Ecosystem Development at Arm, where he helps partners create data center, networking, and edge solutions. Before joining Arm, Eddie worked at AMD, Marvell, Seagate, and Western Digital. He has been a program participant at many worldwide conferences, including CES, Mobile World Congress, and OCP Global Summit. He earned a BSEE from MIT and is a frequent blogger and press interviewee on data center infrastructure.
Abstract: AI is influencing multiple workstreams, all of which have different requirements and outcomes. The diversity of these workloads is accelerating the move to custom silicon that is specialized for specific market needs. Chiplets offer a route to composable SoCs without the limitations seen in a typical silicon supply chain. This presentation will review chiplet strategies in play today, and how the market will realize new business models in the future.
About Arm: Arm technology is defining the future of computing. Our energy-efficient processor designs and software platforms have enabled advanced computing in more than 250 billion chips and our technologies securely power products from the sensor to the smartphone and the supercomputer.
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|  Nitza BasocoTechnology and Market StrategistTeradyne
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| | The Right Testing Strategy Can Save DesignsWednesday, January 22nd - 12:00 - 12:30 PM | About the Speaker: Nitza Basoco is a technology and market strategist at Teradyne, where she focuses on startups, emerging companies, and hyperscalers. She was previously VP Business Development at proteanTecs, a startup in agent-based testing. She has also held leadership positions at Synaptics and MaxLinear. Nitza holds a Master of Engineering degree from MIT.
Abstract: Chiplet-based designs complicate testing and add new urgency to getting it done better and earlier. Developers simply must dispose of bad dies as soon as possible to keep costs and schedules under control. Heterogeneous integration is a particularly expensive and time-consuming new step, while packaging has become much more difficult and much costlier. Good testing is essential to having good silicon at a reasonable price.
About Teradyne: Teradyne is an American automatic test equipment designer and manufacturer based in North Reading, Massachusetts. Teradyne's high-profile customers include Samsung, Qualcomm, Intel, Analog Devices, Texas Instruments and IBM. For more information, see: teradyne.com
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