Thursday, February 8th

Tony Chan Carusone

CTO

Alphawave Semi

Keynote 4: Alphawave Semi

Creating the Connectivity Required for AI Everywhere

Thursday, February 8th - 10:10 - 10:40 AM
About the Speaker: Tony Chan Carusone is CTO at Alphawave Semi, where he focuses on developing IP for communicating and processing information. He is also a professor of electrical and computer engineering at the University of Toronto (Canada). He has over 100 published articles, including 11 award-winning best papers, and holds 7 patents. He has presented at many major conferences including ISSCC and the Custom Integrated Circuits Conference (CICC).and is an IEEE Fellow. He co-authored classic textbooks on “Analog Integrated Circuit Design” and “Microelectronic Circuits”. He earned a PhD in electrical engineering from the University of Toronto.

Abstract: All major semiconductor companies now use chiplets for developing devices at leading-edge nodes. This approach requires a die-to-die interface within packages to provide very fast communications. Such an interface is particularly important for AI applications which are springing up everywhere, including both large systems and on the edge. AI requires high throughput, low latency, low energy consumption, and the ability to manage large data sets. The interface must handle needs ranging from enormous clusters requiring optical interconnects to portable, wearable, mobile, and remote systems that are extremely power-limited. It must also work with platforms such as the widely recognized ChatGPT® and others that are on the horizon. The right interface with the right ecosystem is critical for the new world of AI everywhere.

David McIntyre

Member

SNIA Board of Directors

Special Presentation 3: SNIA

New Standards Control the Data/Storage Tsunami

Thursday, February 8th - 10:40 - 10:50 AM
About the Speaker: David McIntyre is Director Product Planning at Samsung Semiconductor, where he leads product planning and business enablement for computational storage. He focuses on data center cloud to edge acceleration solutions in data analytics, security, and AI. He has been a program participant at the Persistent Memory Summit, Flash Memory Summit, and other forums. Before joining Samsung, he worked at Xilinx on new data center initiatives including blockchain. He has also worked at Intel and Altera where he focused on storage, test, and measurement applications for FPGAs. He earned an MSEE from Ohio University and an MBA from San Jose State University.

Sam Salama

Hyperion Technologies

Keynote 5: Hyperion Technologies

New Packaging Technology Accelerates Major Compute Tasks

Thursday, February 8th - 10:50 - 11:20 AM
About the Speaker: Sam Salama is the CEO of Hyperion Technologies, a manufacturer of microelectronic systems and advanced packaging. His goal is to develop new packaging and heterogeneous integration methods that will lead to more computing power at lower cost. Before founding Hyperion, he was a VP/GM at Intel, managing a $3B annual packaging and high-density interconnect substrate business. His organization led a network of 18 global high-volume factories producing more than 1B units annually. Dr. Salama played a key role in the development of EMIB (Embedded Multi-die Interconnect Bridge) and other Intel packaging and integration products. He holds over 130 patents and has published over 30 technical articles, book chapters, and industry reviews. He earned a PhD in materials engineering from the University of Central Florida.

Abstract: Many rapidly emerging compute applications (especially generative AI) need vast computing power and memory capacity. A new 3D packaging technology (QCIA) offers a highly economical solution. It allows larger packages, much higher power dissipation (up to 1000 watts per package), and substrates that exceed 100 mm by 100 mm (beyond the limitations of silicon interposers and without the warpage issues). For example, a single package could hold compute and SRAM devices plus many high- bandwidth memory (HBM) stacks for AI acceleration. Even more should be possible soon as research into new technologies employing < 1-micrometer line/space redistribution layers and panel-processing technologies for bigger packages continues. The development of materials for systems with even higher power dissipation is also ongoing. The QCIA technology can both help meet thermal challenges and deliver fine-pitch connections. It can provide some of the smaller-better-cheaper progress that Moore’s Law can no longer offer.

Francisco Socal

Arm

Mark Knight,

Arm


Special Presentation 4: Arm

Reusable Chiplets for Heterogeneous Computing

Thursday, February 8th - 11:20 - 11:35 AM
About the Speaker: Francisco Socal is a Director of Product Management in Arm’s Architecture and Technology Group (ATG) for AMBA and other system architectures. He previously worked for Imagination Technologies and Supponor. He has extensive experience in image processing and embedded systems. Francisco earned a Master’s in Information Technology from the Helsinki Metropolia University of Applied Sciences.

About the Speaker: Mark Knight is a Director of Product Management in Arm’s Architecture and Technology Group (ATG) with responsibility for chiplet and security architectures. He previously worked for Microsoft and Thales e-Security. He has extensive experience in security (including confidential computing), scalable cloud computing, and full lifecycle software development. He earned a BS in computer science from the University of Hertfordshire (UK).

Abstract: Achieving the potential of chiplets requires standardization. Well-defined chiplet types and a layered approach to standardization are prerequisites to a vibrant chiplet marketplace. A new family of standards will help designers build reusable chipsets that they can integrate into multiple systems. It will extend the Advanced Microcontroller Bus Architecture (AMBA)’s on-chip Coherent Bus Interface (CHI) to a chip-to-chip (C2C) version suitable for connecting chip(let)-to-chip(let). These initiatives will complement other chiplet standardization work such as UCIe to drive further alignment and collaboration.

Bapi Vinnakota

Open Compute Project

Cliff Grossner,

Open Compute Project (OCP)


Keynote 6: Open Compute Project

Creating a Vibrant Open Chiplet Economy

Thursday, February 8th - 11:35 - 12:05 PM
About the Speaker: Bapi Vinnakota currently leads the Open Domain-Specific Architecture (ODSA) sub-project within the Open Compute Project (OCP). At OCP, he is working on the open chiplet economy, including the Bunch of Wires (BoW) die-to-die interconnect standard. He previously held engineering management positions at Broadcom, Netronome, and Intel. He has several publications on ODSA and BoW, including an invited talk at the ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP), presentations at Hot Interconnects, and an article in IEEE Micro. He earned a PhD in computer engineering from Princeton University.

About the Speaker: Cliff Grossner is Chief Innovation Officer at OCP where he leads its market intelligence and drives new programs including guiding inventors in developing early-stage company ideas, setting strategic direction and building awareness of OCP, establishing new alliances, and launching new activities. Before joining OCP, he headed the Cloud and Data Research Practice at Informa Tech, where he worked on cloud services, data center compute and networking, and data center infrastructure. He previously held senior positions at Alcatel-Lucent, Bell Labs, and Nortel. He earned his PhD at McGill University (Canada) and holds over 10 patents in networking and telecommunications.

Abstract: Chiplets have arrived as the way to design very large chips at leading-edge nodes. But how can we take full advantage of the drop-in approach they offer, allowing designers to easily include existing designs at older nodes, IP, and chiplets from outside sources? The OCP believes that an open chiplet economy is the way to go. It will serve the needs of chiplet creators, ASIC designers, and those providing support such as design tools, test facilities, and professional services. Such an economy requires standards, tools, and best practices. The OCP is already pursuing projects that standardize design models, help establish 3rd party testing, improve supply chain methods, define best practices for assembly, and create a standard high- performance, low-power die-to-die interface. The open chiplet economy will benefit large and small organizations alike, and will create huge opportunities for economic growth worldwide.