Wednesday, February 7th

Charles Sobey

Chiplet Summit

Introduction to the 2024 Chiplet Summit

Chairman Welcome

Wednesday, February 7th - 8:45 - 9:00 AM
About the Speaker: Chuck Sobey is the General Chair of Chiplet Summit. He leads the Organizing Committees and identifies key trends, sessions, and speakers. Chuck is a respected technology strategist/ researcher and President/Founder of the R&D services firm ChannelScience. He helps clients develop and deploy signal processing and coding solutions for emerging memory and storage technologies. He is leading a $1.6M research grant from the US Department of Energy to develop new technology to recover irreproducible scientific data from deteriorating legacy magnetic tapes. Chuck earned an MS in electrical and computer engineering from University of California, Santa Barbara (UCSB) and holds 7 US patents.

Abstract: 2024 will be a growth year – especially for generative AI and chiplets! Start it off right by meeting with the leading chiplet executives and technologists at the 2nd annual Chiplet Summit. You will hear the latest ideas and breakthroughs, see the new products, learn about generative AI acceleration, and exchange ideas with the industry’s innovators. We have a new venue with lots of room for conversations, meetings, demonstrations, and posters. Please join us for pre-conference tutorials (including new ones on working with foundries and AI in chiplet design), a superpanel on accelerating generative AI applications, our popular “Chat with the Experts” event, presentations, and exhibits. You will hear about industry trends at keynotes from Applied Materials, Synopsys, Micron, Alphawave Semi, Hyperion Technologies, and the Open Compute Project. Chiplet Summit is the place where the entire ecosystem meets to share ideas across disciplines and keep the chiplet industry moving ahead. Please join us at this must-attend event!

Subi Kengeri

Applied Materials

Keynote 1: Applied Materials

Systems to Materials Co-optimization in the AI Era – a Critical Need

Wednesday, February 7th - 10:10 - 10:40 AM
About the Speaker: Subi Kengeri is VP AI System Solutions at Applied Materials, where he leads the development of next generation products. He was previously CTO/VP World-Wide Client Solutions at GlobalFoundries and Sr Director/Head TSMC North America Design Center. He holds 47 patents and has given over 100 invited talks and press interviews. He earned an MSEE equivalent at IIT Delhi.

Brian Rea

UCIe Consortium

Special Presentation 1: UCIe Consortium

Enabling an Open Chiplet Ecosystem at the Package Level

Wednesday, February 7th - 10:40 - 10:50 AM
About UCIe Consortium: The UCIe Consortium is an industry consortium dedicated to advancing UCIe™ (Universal Chiplet Interconnect Express™) technology, an open industry standard that defines the interconnect between chiplets within a package, enabling an open chiplet ecosystem and ubiquitous interconnect at the package level. UCIe Consortium is led by key industry leaders Advanced Semiconductor Engineering, Inc. (ASE), Alibaba, AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, NVIDIA, Qualcomm Incorporated, Samsung Electronics, and Taiwan Semiconductor Manufacturing Company. For more information, visit www.UCIexpress.org.

Abhijeet Chakraborty

Fellow

Synopsys

Keynote 2: Synopsys

Multi-Die Systems Set the Stage for Innovation

Wednesday, February 7th - 10:50 - 11:20 AM
About the Speaker: Abhijeet Chakraborty is VP Engineering at Synopsys, where he is responsible for the EDA technology roadmap, driving 3D heterogeneous integration in government programs, and cloud solutions. He has also held senior engineering R&D leadership roles at the highly regarded startups Magma Design Automation and Monterey Design Systems. He has been active in promoting multi-die systems through his work with the MITRE Engenuity task force. He has participated in many conferences, including DAC and ECTC, and holds several patents. He earned an MSEE from the University of Texas at Austin.

Abstract: So far, the only design teams able to handle multi-die systems are bleeding-edge ones accustomed to breaking new ground with every step. Now the ecosystem is providing the tools, IP, standards, connectivity, and manufacturing needed to allow many more teams to switch to this new approach. Multi-die systems are now the mainstream and open up innovation in AI, security, transaction systems, virtual reality, and other areas. They continue the trend established by Moore’s Law to provide more compute power, more memory and storage, and faster I/O in less space and at lower cost.

Nick Kepler

Silicon Catalyst

Special Presentation 2: Silicon Catalyst

Accelerating Chiplet Startups

Wednesday, February 7th - 11:20 - 11:30 AM
About the Speaker: Nick Kepler has over 30 years of experience in the semiconductor industry, with varied leadership and technology management roles including semiconductor process technology development and manufacturing, design enablement, technical program management, and customer-facing marketing and technical sales. Prior to Silicon Catalyst, Nick was VP of Products for SuVolta, a startup developing semiconductor technology IP. Prior to SuVolta, Nick was VP of Corporate Program Management and previously VP of Design Enablement at GLOBALFOUNDRIES. Nick spent 23 years at AMD in a variety of management and technical roles concluding with VP, Advanced CMOS Process Technology Development. Nick has BS and MS degrees in EECS from the University of California at Berkeley.

Gurtej Sandhu

Micron

Keynote 3: Micron

Future of Memory Chip Technology

Wednesday, February 7th - 11:30 - 12:00 PM
About the Speaker: Gurtej Sandhu is Principal Fellow and CVP at Micron Technology. In his current role, he is responsible for Micron’s end-to-end (Si-to-Package) R&D technology roadmaps. The scope includes driving cross-functional alignment across various departments and business units to proactively identify technology gaps and managing the engineering organization to resource and execute on developing innovative technology solutions for future memory scaling. Dr. Sandhu’s responsibilities include driving state of the art methodologies to help develop complex technologies faster and more efficiently and managing interactions with research consortia around the world. Dr. Sandhu received a degree in electrical engineering at the Indian Institute of Technology, New Delhi, and a Ph.D. in physics at the University of North Carolina, Chapel Hill.. He is a Fellow of IEEE and recognized as one of the top inventors in the world. In 2018, he received the IEEE Andrew S. Grove Award for outstanding contributions for DRAM and NAND memory chip scaling.

Abstract: A commitment to innovation and creativity at a system level is required to meet demands of this data age. These innovations will help fuel the next generation of capabilities in generative artificial intelligence (GenAI) and enable technologies such as self-driving cars, smart medicine, industrial automation, space exploration etc. which sounded like science fiction not so long ago. Several new memory technologies have been proposed over the years with no clear winners. Some of the critical factors which need to be considered for a successful implementation of a new technology include why and when alternate memory technologies may be needed, what are the performance criteria and related requirements, and what needs to happen in the ecosystem to support a successful new technology. The result of this reality is that bottoms up development for a new memory technology may not feasible and we must target application-specific solutions for future markets.