| Thursday, February 8th |
Thursday, February 8th
9:00-10:00 AM | | A-201: Design - 3 (Design/Security Track) | | Moderator: Feng Zhou, Sr Technical Staff, Silicon Storage Technology | Paper Presenters:
| Early Predictive Mechanical Analysis Workflow for Chiplet-Based Designs
Subramanian Lalgudi, , Siemens EDAModel-Based System Design for Chiplet-Based Architectures - Click for Proceedings:
Denis Dutoit, Program Manager, CEA-ListUsing a System-Level Model to Evaluate Heterogeneous Chiplet Architectures - Click for Proceedings:
Deepak Shankar, Vice President Technology, MIRABILIS DESIGN | Session Description:
| Having the right tools is surely the key to successful chiplet-based design. System-level models have become essential in all cases since emulation hardware is seldom available. They allow designers to experiment with different decisions and see what happens. Even long runs are better than waiting for prototypes to be built and tested. Special software is also necessary to handle non-electrical issues, such as power, thermals, and mechanical design. Of course, such tools must be updated to operate in the chiplet world rather than the traditional monolithic designs.
| | About the Organizer/Moderator: | Feng Zhou is a senior member of technical staff at Microchip Technology. He holds 22 patents. He earned a PhD in Materials Science and Engineering at the University of Texas Austin.
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Thursday, February 8th
9:00-10:00 AM | | B-201: Integration - 1 (Interfaces - Integration - Applications Track) | | Moderator: Mark Berry, President, COT-NPI Group | Paper Presenters:
| Wafer Level Technologies for Heterogeneous Chiplet Integration - Click for Proceedings:
Sylvie Joly, Partnerships Manager 3D Integration and Packaging, CEA-ListEvaluating Technical Approaches to Heterogeneous Integration
Nicolas Pantano, Principal MTS, imecExtending Chiplet-Based Solutions from 2.5D to 3D
Igor Elkanovich, CTO, Global Unichip (GUC) | Session Description:
| Heterogeneous integration is surely the most difficult stage of chiplet development. It involves everything from ensuring that the chiplets actually fit in the package in the right order through power and thermal analysis. The designers must optimize everything together (so-called co-optimization) and manage to create a manufacturable device. The system-in-chip itself requires a controller to manage both control signals and data. One option is to use an FPGA chiplet to produce the needed signals. There are currently many approaches designers must evaluate carefully to get the right fit for their applications.
| | About the Organizer/Moderator: | Mark Berry is an independent consultant in test strategies, operations, and business development. He is also a contributing editor to the popular 3DInCites Website. His consulting clients have included PDF Solutions, Caliber Interconnects, Sonic Energy, and UTAC. He focuses on lower test costs, accelerating new product introduction, test strategies and roadmaps, advanced packaging, and test sales and business development. He has 15 years experience as a VP in test technology with Amkor and 15 years as a test manager with Freescale Semiconductor. Mark earned a BSEE from the University of Illinois at Urbana-Champaign and an MBA from St. Edward’s University (Austin, TX).
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Thursday, February 8th
9:00-10:00 AM | | C-201: Making Chiplets a Viable Market (sponsored by SmartSoC Solutions) (Panel Track) | | Organizer + Moderator: Ravi Agarwal, Director Technology Pathfinding, Meta | Panel Members:
| Panelist: Ramin Farjad, CEO, EliyanPanelist: Kevin Yee, Sr Director, Samsung SemiconductorPanelist: Wolfgang Sauter, , MarvellPanelist: Clint Walker, VP Marketing, Alphawave Semi | Session Description:
| Many articles have raised the idea of designers being able to shop for the chiplets they want in a marketplace and then simply drop them into their designs. Obviously, such a concept depends on a viable market in which chiplet designers can make a return on their investment. Clearly it would require standards for chiplets so designers would know what they’re getting and how it would integrate into their devices. Each chiplet must carry information about its connections and characteristics in a specific form. The chiplet would also have to pass both security and interoperability tests. Clearly such a marketplace will take time to develop and will require an organization to oversee it.
| | About the Organizer/Moderator: | Ravi Agarwal is a Technical Sourcing Manager at Meta, where he focuses on chiplet strategy, advanced packaging architecture, supply chain, strategic sourcing, and open ecosystem development. He also is the Chair of the IEEE Electronic Packaging Society’s Silicon Valley chapter and the Lead of the ODSA Chiplet Business Working Group. He was previously Director of Strategy and Chief of Staff for a Corporate VP at Intel and Director of Product Management at Amkor. He earned a PhD in Materials Science and Engineering at North Carolina State University and an MBA from UC Berkeley. He has 14 published papers and holds three patents.
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Thursday, February 8th
2:00-3:20 PM | | A-202: Design - 4 (Design/Security Track) | | Moderator: Pratyush Kamal, 3DIC Solutions Architect, Siemens EDA | Paper Presenters:
| Controlling Production Test Costs for Chiplet-Based Design - Click for Proceedings:
Vineet Pancholi, Sr Director Test Technology, AmkorProtecting Against ESD in Die-to-Die Interfaces - Click for Proceedings:
Bart Keppens, Chief Business Development, SoficsFunctional Simulation and Verification Workflow for Chiplet-Based Systems
James Wong, CTO, Palo Alto ElectronJawad Nasrullah,
CEO,
Palo Alto Electron
| Session Description:
| Chiplets create many new issues for designers. Functional simulation and verification must now allow for multiple chiplets as well as interconnections and chiplet-chiplet interaction. Test becomes much more complex, with chiplets having to be tested individually, interconnections requiring tests, and the entire device requiring testing as a whole. New tools and procedures are necessary, and the time allotted for steps must be increased. Schedules will also surely lag unless steps such as packaging, test, and integration are not started early in the process.
| | About the Organizer/Moderator: | Pratyush Kamal is a 3DIC Solutions Architect at Siemens EDA. An experienced silicon to systems architecture and technology lead, he previously worked at Google and Qualcomm. He has 3 publications and holds 20 patents. He earned a BSEE equivalent at IIT Delhi.
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Thursday, February 8th
2:00-3:20 PM | | B-202: Best Packaging for Chiplets Today (Panel) (Panel Track) | | Moderator: Paul Franzon, Professor, North Carolina State University | Panel Members:
| Panelist: Daniel Lambalot, Sr Principal Package Designer, Alphawave SemiPanelist: Nokibul Islam, Director Group Technology Strategy, JCET GroupPanelist: Laura Mirkarimi, VP 3D Techologjes, AdeiaPanelist: Atom Watanabe, Research Staff Member, IBM Research | Session Description:
| Packaging is one of the most difficult areas for chiplet designers. Packages must be capable of handling power and heat dissipation, be reasonably priced and small, and be rugged enough for standard applications. Issues of concern include who selects the package and how, which packages are best-suited to chiplet-based designs, what breakthroughs we can expect in packaging over the next few years, and what are the best tradeoffs among size, performance, features, and cost for the many types of packages available today.
| | About the Organizer/Moderator: | Paul Franzon is a professor and Director of Graduate Programs at North Carolina State University (NCSU). He is also the Site Director Center for Advanced Electronics through Machine Learning (CAEML). A well-known researcher, he has over 400 published papers in such journals as IEEE Transactions on VLSI Systems, IEEE Transactions on Circuits and Systems, and IEEE Electron Device Letters and at important conferences such as ECTC, 3DIC, IEDM, ICCAD, EPEPS, and SOCC. He has also written books and contributed chapters to them. Before joining the NCSU faculty, he worked at AT&T Bell Laboratories and Australia Telecom. He has also founded four technology companies. He earned a PhD from the University of Adelaide (Adelaide, Australia). He is an IEEE Fellow and has received many research and teaching awards.
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Thursday, February 8th
2:00-3:20 PM | | C-202: Chiplets for Entrepreneurs - Making Money in the Chiplet Game (Panel Track) | | Moderator: Vince Kohli, Tech Entrepreneur, Impact VC | Panel Members:
| Panelist: Tarun Verma, Managing Partner, Silicon CatalystPanelist: Stephen Slater, EDA Product Manager, Keysight Technologies InternationalPanelist: Vincent (Woopoung) Kim, cEVP, SamsungPanelist: Scott Best, Technical Director, RambusPanelist: Keith Witek, COO, TenstorrentPanelist: Brian Faith, CEO, QuickLogic | Session Description:
| Surely the obvious way to make money from chiplets is to build them. Most likely candidates are ones that have good-sized markets but require special expertise. Possibilities include financial algorithms, video encoding, mathematical functions, compression methods, noise reduction methods, or security. Still others might include functions of value in specific occupations such as accounting, insurance, or engineering. Still other ways to make money include offering chiplet development or test services, creating platforms for building chiplets, producing unusual devices such as special interposers, and providing accelerators for game players or financial analysts.
| | About the Organizer/Moderator: | Vince Kohli is a private investor/advisor specializing in early-stage startups. He works with startups in areas ranging from bioengineering, life sciences, and pharma through blockchain, NFTs, and metaverse. His aim is to make companies public in 7 years or less and outperform other early-stage participants. He also serves as a startup judge for both Google and Stanford University and has been a business advisor for Facebook and Microsoft. He has raised over $800 million in venture money for companies in the program with which he works. He earned an MBA from the Wharton School in entrepreneurship and entrepreneurial studies.
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Thursday, February 8th
3:30-4:50 PM | | B-203: Chiplets in 2029 and How We Got There (Panel) (Panel Track) | | Organizer: Paul Borrill, Chief Product Officer, DaedaelusModerator: Bill Wong, Technology Editor, Electronic Design | Panel Members:
| Panelist: Tom Hackenberg, Principal Analyst, Yole GroupPanelist: Bapi Vinnakota, ODSA Project Lead, Open Compute ProjectPanelist: Sridhar Valluru, Director Product Management, ArmPanelist: Jawad Nasrullah, CEO, Palo Alto Electron | Session Description:
| The five-year horizon for chiplets is very promising. They will make up an ever increasing part of the large chip market, as their cost is more than balanced by the tremendous advantages they bring to chip design and development. More development platforms, operating systems, utilities, and other tools will be available for them. Standardization will be a major issue, as most large customers will want multiple sources as well as large ecosystems and wide support for both development and test. Other issues include achieving higher throughput and lower latency, isolating executing applications from one another, security, and EDA, packaging, integration, and test platform support.
| | About the Organizer/Moderator: | Paul Borrill is founder and Chief Product Officer of Daedaelus and a leading industry expert on resilient network and storage infrastructures. He has been a major contributor to modern infrastructure development at such technology-leading companies and organizations as NASA, Apple, Sun Microsystems, and Quantum. Paul was cofounder of the Hot Interconnects conference and founding chair of the Storage Networking Industry Association (SNIA). Paul was also VP Technical Activities and VP Standards for the IEEE Computer Society, the leading worldwide technical society for computer engineering. Paul earned a PhD in Physics from University College London. He has presented at many conferences on distributed systems and holds nine patents in that area.
Bill Wong is Editor of Electronic Design Magazine, as well as Senior Content Director of its parent organization, Endeavor Business Media. One of the best-known editors in the technical press, he is noted for his interviews, analysis, and project articles. He focuses on embedded, software, and systems applications in the magazine. He has solid technical credentials, having earned a BSEE at Georgia Tech and an MSCS at Rutgers. He still works on hardware and software projects, including C, C++, and PHP programming and hardware ranging from robotics to AI systems.
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