Wednesday, February 7th
Wednesday, February 7th
9:00-10:00 AM
Chiplets: Where We Are Today (Plenary Track)
Paper Presenters:
Chiplet Markets Are Rising: Where and When? - Click for Proceedings:
Tom Hackenberg, Principal Analyst, Yole Group

Ying-Wu Liu, Technology/Cost Analyst, Yole SystemPlus
Developing Chips for Tomorrow: You, Me, and ChatGPT - Click for Proceedings:
Jawad Nasrullah, CEO, Palo Alto Electron

Session Description:
Chiplets allow designers to break up the design of large chips into smaller units. The advantages are shorter design time, lower cost, easier drop-in inclusion of already available designs, increased modularity and scalability, and fewer manufacturing defects. Chiplets allow for ready inclusion of analog and other accessory circuits, proven designs from previous nodes, and designs from other technologies. Obviously, the major issue is integrating all the chiplets together. This requires high-speed buses to avoid latency and maximize throughput, interconnection patterns, and often an interposer to provide connections between chiplets. The drop-in approach should eventually lead to a large ecosystem including chiplet libraries, IP, stores, and exchanges.
About the Organizer/Moderator:
Wednesday, February 7th
2:00-3:00 PM
A-101: Security - 1 (Design/Security Track)
Moderator: John Ferguson, Principal Engineer, Siemens EDA

Paper Presenters:
Developing Secure Multi-Die Systems - Click for Proceedings:
Dana Neustadter, Product Management Director, Synopsys

Using Functional Monitors to Ensure Chiplet Integrity - Click for Proceedings:
Lee Harrison, Marketing Director, Siemens Digital Industries Software

Session Description:
Security is a major challenge for chiplet-based designs. Vulnerabilities can occur at the chip or chiplet level. They may also occur in the die-to-die interfaces, packaging, and other circuitry including power and clock distribution. Even more problems can occur if chiplets are from different manufacturers, processes, or substrates. Security standards will be essential if an open chiplet economy is to be achieved.
About the Organizer/Moderator:
John Ferguson is Director Product Management at Siemens EDA where he is in charge of the Calibre nmDRC and 3DIC physical management tools. He holds several patents and is the author of many articles and blogs on physical design and verification design. He has also presented at many conferences, including Chiplet Summit. He earned a PhD in Electrical Engineering from the Oregon Graduate Institute of Science and Technology (Portland, OR).

Wednesday, February 7th
2:00-3:00 PM
B-101: Interfaces - 1 (Interfaces - Integration - Applications Track)
Moderator: Dharmesh Jani, Open Source Ecosystem Leader, Meta

Paper Presenters:
Using a Simulation Model to Optimize UCIe Implementations - Click for Proceedings:
Hee-Soo Lee, High-Speed Design Lead, Keysight Technologies

Adrian Auge, Sr Staff Signal Integrity Engineer, Alphawave Semi
Fangyi Rao, , Keysight Technologies
UCIe Reaches a First Step in Interoperability - Click for Proceedings:
Manuel Mota, Sr Product Manager, Synopsys

eFPGA Solutions for Flexible Die to Die Protocol Adapters - Click for Proceedings:
Nick Ilyadis, VP Product Planning, Achronix

Session Description:
The die-to-die interface connecting chiplets is critical to chiplet-based design. It must be extremely fast, highly reliable, and very flexible. It must also be low-power and take little chip area. There are two major contenders: Universal Chiplet Interface Express (UCIe) from the UCIe Consortium and Bunch-of-Wires (BoW) from the Open Compute Platform Foundation. Issues include the development of interface controllers, achieving interoperability, and developing models that allow designers to try out options and see how they perform.
About the Organizer/Moderator:
Dharmesh Jani is Infrastructure Ecosystem/Partnership Lead at Meta, where he drives strategic technology engagement with the industry and the open source community. He is co-chair of the Incubation Committee at Open Compute Project, driving the organization’s vision for the data center. He is also a member of the board of directors of the Universal Chiplet Interface Express (UCIe) Consortium which is developing a die-to-die interface for chiplets. He has presented at many conferences, including OCP Summit and Chiplet Summit. Before joining Meta, he was a VP at Flex, where he drove technology innovation. He earned an MSEE at UCLA.

Wednesday, February 7th
2:00-3:00 PM
C-101: Chiplets Drive Top Leading-Edge Designs (Panel Track)
Organizer + Moderator: Arvind Kumar, Principal Research Staff Member, IBM

Panel Members:
Panelist: Anu Ramamurthy, Associate Technical Fellow, Microchip

Panelist: Denis Dutoit, Program Manager, CEA-List

Panelist: Jinho An, Account Technologist Director, Applied Materials

Panelist: Helia Naeimi, Director, Tenstorrent

Panelist: Kenneth Larsen, Director Product Management, Synopsys

Panelist: Suresh Ramalingam, Corporate Fellow, AMD

Session Description:
Chiplets are currently the best answer to the increasing demands of applications such as generative AI. However, many issues arise in using them in the quest for more processing power at the right price. New architectures are necessary to bring compute closer to memory, preferably within packages to reduce transit delays. New packages are needed to allow higher power ratings, more conductive area, and faster interconnections. Testing and integration must occur in parallel with design to meet schedules and reduce time-to-market. And standardized chiplets must be readily available, easy to use, and highly reliable and secure. The entire process must also be usable for a wide range of applications with different cost structures, volumes, and environmental and lifetime requirements.
About the Organizer/Moderator:
Arvind Kumar is a manager of AI Hardware Technologies at the IBM Thomas J. Watson Research Center. His research focuses on the requirements of AI systems and the heterogeneous integration innovations to accelerate them. He has presented several invited talks and served as a panelist and short-course instructor in this area at major conferences. He holds 30 patents and is an IBM Master Inventor. He has published articles in such journals as ACM Journal on Emerging Technologies in Computing Systems and Solid State Physics. He earned a PhD in Electrical Engineering and Computer Science from MIT.

Wednesday, February 7th
2:00-3:00 PM
D-101: Annual Update on Packaging (Annual Update Track)
Moderator: Nathan Brookwood, , Insight 64

Paper Presenters:
Annual Update on Packaging
Mike Kelly, VP Chiplets and Avanced FCBGA Packaging, Amkor

Session Description:
Chiplet packaging depends on heterogeneous integration of multiple chiplets into a single chip. The package must support a variety of devices, based on different process nodes, substrates, and technologies. It must also provide sufficient heat flow to maintain normal operating temperatures. And it must allow for the interconnections and support mechanisms such as interposers needed to create a viable system. Today’s advanced packages increase system-level interconnection density, reduce power consumption, integrate more functions, lower cost, and achieve larger sizes.
About the Organizer/Moderator:
Nathan Brookwood is Research Fellow at Insight 64, a semiconductor consulting firm. He has focused recently on microprocessors used in computational applications. His views on the microprocessor market often find their way into articles in mainstream media, business media, and the trade press. He has worked for and with suppliers of mainframes, minicomputers, personal computers, and semiconductors, and he has analyzed and commented on the industry for D.H. Brown Associates and Dataquest. He is a graduate of MIT.

Wednesday, February 7th
3:15-4:15 PM
A-102: Design - 1 (Design/Security Track)
Moderator: Siamak Tavallaei, , CXL Consortium

Paper Presenters:
Hierarchical Approach to Multiphysics Analysis of Chiplet-Based Designs - Click for Proceedings:
Lang Lin, Principal Engineer, Ansys

Using Integrated Voltage Regulators in Chiplet Designs - Click for Proceedings:
Trey Roessig, CTO and SVP Engineering, Empower Semiconductor

Early Predictive Power Integrity Analysis for Chiplet-Based Designs - Click for Proceedings:
Subramanian Lalgudi, , Siemens EDA

Session Description:
Chiplet-based design requires many new and upgraded tools. The usual analysis and verification platforms must be extended to handle multiple chiplets and data must be managed. All of this is complicated by the need to apply everything both to individual chiplets and to the package as a whole. Runtimes will lengthen for entire packages, and the number of runs obviously depends directly on the number of chiplets. Drop-in chiplets can help reduce the strain if methods can be developed for assuring their characteristics and performance. Power is also a problem, since it must be distributed properly among chips with varying requirements and often high demands.
About the Organizer/Moderator:
Siamak Tavallaei is an independent Chief Systems Architect instrumental in developing servers, computing elements, interconnects, and distributed computers. He has been a Chief Systems Architect at Google, a Principal Architect at Microsoft, and a Chief Architect at HP. He is an advisor to the Board and former President of the CXL Consortium, which is developing a high-speed processor-to-memory interface. He has also been active at OCP, where he was a co-lead of the Server Project and received the 2021 Leadership Award. He has over 50 registered patents in computer server architecture, design, and fault management, as well as many publications and conference appearances. He earned an MSEE at Utah State University.

Wednesday, February 7th
3:15-4:15 PM
B-102: Applications - 1 (Interfaces - Integration - Applications Track)
Moderator: Nokibul Islam, Director Group Technology Strategy, JCET Group

Paper Presenters:
Chiplets Enable New Heterogenous Compute Architectures - Click for Proceedings:
Philip Lewer, Sr Product Director, Untether AI

Multi-Die Systems for Aerospace and Defense Applications - Click for Proceedings:
Ian Land, Sr Solutions Director, Synopsys India

Chiplet-Based Modular Servers Meet Many Application Needs - Click for Proceedings:
Paul Borrill, Chief Product Officer, Daedaelus

Session Description:
The chiplet approach can serve a wide range of applications. One popular example is driver-assistance systems for vehicles. Furthermore, the chiplet substructure may itself be dynamically reconfigurable to allow system changes for clouds where the mix of applications is constantly changing.
About the Organizer/Moderator:
Nokibul Islam is Sr Director Field Applications Engineering at JCET Group, where he focuses on semiconductor packaging technology, product development, qualification, product management, and marketing. Before joining JCET Group, he was an engineer at Amkor. He has published many papers on electronic packaging design and has presented at many conferences including IMAPS, ECTC, and DPC. He has been a program committee member for many conferences and is the General Chair for the 19th Annual Device Packaging Conference (DPC 2023). He earned a PhD in mechanical engineering from Auburn University (AL).

Wednesday, February 7th
3:15-4:15 PM
C-102: Next Great Breakthrough in Chiplets (Panel) (Panel Track)
Moderator: Milind Weling, Head Neuromorphic Realization, EMD Electronics

Panel Members:
Panelist: Mark Knight, Director Product Management, Arm

Panelist: Nir Sever, , ProteanTecs

Panelist: Nitza Basoco, , Teradyne

Panelist: Jim Finnegan, COO, Netronome

Panelist: Jean Bozman, President, Cloud Architects

Session Description:
Many important changes will surely occur in the emerging chiplets arena. They may include new combined packages that allow designers to co-optimize chiplets from the partitioning stage through integration and test. Other possible advances could include standards that allow for portability of chiplets between applications, better test tools and interposers, interoperability testing, optical interfaces, and exchanges or chiplet stores that allow designers to readily find what they need from a variety of sources.
About the Organizer/Moderator:
Milind Weling is the Head of Neuromorphic Realization and co-founder of the Neuromorphic Computing incubator of EMD Electronics, a business of Merck KGaA Darmstadt Germany. Previously he led Customer Programs and Operations for Intermolecular, where he drove the discovery and optimization of new materials, integrated module solutions, and leading edge devices. Milind has extensive experience in advanced memory and logic technology development, DFM and design-process interactions, new product introduction, and foundry management. He previously held senior engineering and management positions at Cadence Design Systems, Sun Microsystems, Philips Semiconductors, and VLSI Technology. Milind earned an MSEE at the University of Hawaii. He holds 50+ patents and has co-authored over 70 technical papers, primarily focused on semiconductor process technology, device reliability, and integration.

Wednesday, February 7th
3:15-4:15 PM
D-102: Annual Update on Die-to-Die Interfaces (Annual Update Track)
Moderator: Nathan Brookwood, , Insight 64

Paper Presenters:
Annual Update on Die-to-Die Interfaces
Letizia Giuliano, VP IP Product Marketing/Management, Alphawave Semi

Session Description:
The common interfaces for chiplet design today are BoW (Bunch of Wires) from the Open Compute Project (OCP) and UCIe (Universal Chiplet Interface Express) from the UCIe Consortium. Both are open standards that support many architectures and have emerging ecosystems. Both have governing bodies that issue extensions and revisions and provide training, education, and other support.
About the Organizer/Moderator:
Nathan Brookwood is Research Fellow at Insight 64, a semiconductor consulting firm. He has focused recently on microprocessors used in computational applications. His views on the microprocessor market often find their way into articles in mainstream media, business media, and the trade press. He has worked for and with suppliers of mainframes, minicomputers, personal computers, and semiconductors, and he has analyzed and commented on the industry for D.H. Brown Associates and Dataquest. He is a graduate of MIT.

Wednesday, February 7th
4:30-5:30 PM
A-103: Design - 2 (Design/Security Track)
Moderator: Denis Dutoit, Program Manager, CEA-List

Paper Presenters:
Powering Chiplet-Based Designs with Integrated Bucket Converters - Click for Proceedings:
Dan Kultran, CTO, Epirus

Reducing Upfront Costs to Accelerate Chiplet Adoption - Click for Proceedings:
Kash Johal, CEO, YorChip

Session Description:
Chiplet-based design can be a long, time-consuming process. Each chiplet may require separate circuitry for such basic functions as power, clocking, and thermal protection. One possible approach to avoid all this extra work is to create a family of proven chiplets that designers can use to create complex chips. This approach provides many of the advantages of chiplets without all the work. One may compare it to building structures with prefabricated units or Legos rather than from scratch. The question is whether the resulting chips can handle applications well enough to be worth even the reduced time and trouble. Chiplets also raise many new issues. Power must be distributed everywhere to chiplets that may require a variety of voltages and may need substantial currents.
About the Organizer/Moderator:
Denis Dutoit is senior program manager for advanced computing and digital architectures at CEA-List, one of the world’s largest organizations for research in microelectronics. He coordinated the European ExaNoDe project that developed a computer node demonstrator combining chiplets, an active interposer, and bare dies in a System-in-Package (SiP). He has also contributed to the architecture of the European Processor Initiative (EPI). His current focus is on exploring chiplet-based designs for automotive electronics. Before joining CEA, he was a system-on-chip architect at ST Microelectronics and ST Ericsson. He has authored or coauthored more than 20 articles, including invited talks and tutorials at IEEE conferences. He earned a PhD in signal processing from Telecom Paris (ENST).

Wednesday, February 7th
4:30-5:30 PM
B-103: Interfaces - 2 (Interfaces - Integration - Applications Track)
Moderator: Nick Ilyadis, VP Product Planning, Achronix

Paper Presenters:
Efficient Transport in Chiplet-Based AI/ML Applications - Click for Proceedings:
Frank Schirrmeister, CEO, Arteris IP

Guillaume Boillet, VP Solutions & Business Development, Arteris IP
Taking Full Advantage of UCIe in Chiplet Design - Click for Proceedings:
Luis E. Rodriguez, Solutions Architect, Siemens EDA

New Approach to Die-to-Die Memory Chiplet Interconnect - Click for Proceedings:
Ramin Farjad, , Eliyan

Optical Chiplets Meet the Demands of AI Compute Clusters - Click for Proceedings:
Jeff Hutchins, Director CTO Office, Ranovus

Hojjat Salemi, Chief Business Development Officer, Ranovus

Session Description:
Interconnect within a package is a new feature of chiplet design. UCIe and BoW are examples of die-to-die interfaces developed specifically for that purpose. Network- on-chip (NoC) approaches are also available. Still another approach is to connect processors to memory directly without using an interposer.
About the Organizer/Moderator:
Nick Ilyadis is VP Product Planning at Achronix, a leading maker of high-performance FPGAs. He works on next generation FPGA solutions for products and customers in networking, 5G, data center, and automotive applications. A long-time technical leader in the networking area, he previously worked at Marvell, Broadcom, Nortel, and DEC. A prolific inventor with 75 patents, he has written many articles and whitepapers and has presented at such conferences as the IEEE SuperComputer, Chiplet Summit, and SmartNICs Summit. He earned an MSEE in VLSI engineering from the University of New Hampshire.

Wednesday, February 7th
4:30-5:30 PM
C-103: Best Way to Optimize Chiplets (Panel) (Panel Track)
Moderator: Jean Bozman, President, Cloud Architects

Panel Members:
Panelist: Sridhar Valluru, Director Product Management, Arm

Panelist: Philip Lewer, Sr Product Director, Untether AI

Panelist: Mick Posner, VP HPC Interfaces, Synopsys

Panelist: Shahab Ardalan, VP Engineering, Enosemi

Panelist: Elad Alon, CEO, Blue Cheetah Analog Design

Panelist: Jeff Twombly, VP Business Development, Credo Semiconductor

Session Description:
Chiplet optimization may involve many approaches. Power demands can be reduced by lowering voltage levels or reducing operating frequencies. Throughput can be increased by using faster interfaces or shortening distances between devices. Other approaches include using optical interconnect instead of electrical, using faster memory technologies such as MRAM, or avoiding structures such as interposers which slow down signals.
About the Organizer/Moderator:
Jean Bozman is President/Principal Analyst at Cloud Architects, a research and consulting firm focused on cloud infrastructure. She is an expert industry analyst with over 20 years of experience focused on the worldwide IT markets for databases, servers, storage, and software. Her primary focus is analyzing the technologies and market opportunities for data center infrastructure, including both cloud and enterprise data centers. She is well-known from her long stint as IDC’s Research VP and primary analyst on servers. She is a frequent participant at conferences such as Flash Memory Summit and is often quoted in the trade and technical press, including BusinessWeek, Investor’s Business Daily, Bloomberg, and Reuters. She earned an MA from Stanford University.

Wednesday, February 7th
4:30-5:30 PM
D-103: Annual Update on Chiplet Design - Key Challenges and How to Meet Them (Annual Update Track)
Moderator: Joshua Rubin, Sr Engineer, IBM Research

Panel Members:
Panelist: Stephen Wong, , Intel

Panelist: Letizia Giuliano, VP IP Product Marketing/Management, Alphawave Semi

Panelist: Pedro Merlo, Manager Strategic Planning, Keysight Technologies

Panelist: Javier DeLaCruz, Fellow/Sr Director Integration, Arm

Session Description:
Chiplet based designs have progressed rapidly in recent years, however, most designs are sourced by a single vendor. Numerous questions remain about enabling a chiplet ecosystem. This panel will address some of the challenges for interoperability and testing between different vendors for D2D interfaces, tiers of compliance for ensuring an interoperable ecosystem, and test and debug of D2D interfaces. Furthermore, do we need to certify only the end-points (chiplets) or also the interconnect? What are the challenges of defining a common set of rules to ensure an open ecosystem while allowing technology innovation?
About the Organizer/Moderator:
Joshua Rubin is a Sr Engineer at IBM, where he has been technical lead on projects dealing with wafer scale 3D integration, system performance analysis for novel technical elements, heterogeneous integration, and AI hardware design. An IBM Master Inventor, he holds over 75 patents in transistor design and integration, power distribution, 3D integration, packaging, and memory devices. He earned a PhD in electrical engineering at Cornell University. He has also published several technical articles and presented at several conferences including the Electronic Components and Technology Conference (ECTC).