| Tuesday, February 6th |
Tuesday, February 6th
8:30 AM-12:00 PM | | Pre-Conference Tutorial A: Chiplet Basics (Pre-Conference Tutorials Track) | | Moderator: Amy Leong, Member Board of Directors, Skywater TechnologyOrganizer: Anu Ramamurthy, Staff Engineer, Microchip | Paper Presenters:
| Chiplet Packaging Basics
Trent Uehling, Technical Director, NXP SemiconductorsChiplet Testing Basics
Arun Kumar, Sr Staff R&D Engineer, SynopsysIntegrating Chiplets into Large SiP Systems
David Ratchkov, CEO, Thrace SystemsChiplet Design Basics
Surya Kareenahalli, Sr Principal Engineer, IntelChiplets: A New Approach to Better Chips at Smaller Dimensions
Anu Ramamurthy, Staff Engineer, Microchip | Session Description:
| Chiplets let designers develop leading-edge chips more efficiently. The idea is to divide a large SoC into building blocks (or chiplets). They are essentially drop-in pieces of IP, which designers can build, buy or reuse from previous designs. They may come from older process nodes, use new technologies (rather than standard CMOS), or include analog, optical, or other peripheral circuits. Combining the pieces is known as Heterogeneous Integration. It requires a high-speed die to die interface such as Bunch-of-Wires (BoW) or Universal Chiplet Interface Express (UCIe). Designing with chiplets starts with intelligent choices for dividing up the SoC. Chiplets also require complex platforms that offer cross-boundary optimization and support partitioning, validation, packaging, integration, and test. The results are lower manufacturing cost, shorter time-to-market, and better use of resources. The future of chiplets is bright. We will see new platforms, new interfaces, new packages, and new approaches to all development stages. Chiplets are already the way in which all major chipmakers are implementing processors, DPUs, AI chips, communications devices, and ASICs.
| | About the Organizer/Moderator: | Amy Leong is a member of the Board of Directors of Skywater Technology, a pure-play foundry and advanced packaging supplier based in the US. She's an accomplished C-level executive with 25+ years of progressive leadership experience, including General Manager, global sales, applications and services, corporate communications, and mergers and acquisitions. Most recently, Amy was Senior Vice President/Chief Commercial Officer at FormFactor, a maker of semiconductor test and measurement equipment. Before joining FormFactor, she worked at Gartner, KLA and IBM. She has been active at conferences including Semiconductor Wafer Test Workshop, Semicon, International Semiconductor Executive Summit. She earned her Master degree in material science and engineering from Stanford and BS in chemical engineering from UC Berkeley.
Anu Ramamurthy is an Associate Technical Fellow at Microchip Technology, where she works on heterogeneous integration and advanced packaging. She also has expertise in physical design and procurement management of 3rd party IP. Before joining Microchip, she worked at Microsemi and Vitesse Semiconductor as a design engineer and engineering manager. She earned an MS in semiconductor devices from North Carolina State University. She has been an organizer, presenter, and Organizing Committee member for Chiplet Summit.
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Tuesday, February 6th
8:30 AM-12:00 PM | | Pre-Conference Tutorial C: Advanced Packaging Methods (Pre-Conference Tutorials Track) | | Moderator: Atom Watanabe, Research Staff Member, IBM ResearchOrganizer: Laura Mirkarimi, VP 3D Techologjes, Adeia | Paper Presenters:
| Taking Advantage of Hybrid-Bonded Chiplets in Designs
Thomas Workman, Distinguished Integration Engineer, AdeiaChoosing the Right Package for Your Chiplet Application
Craig Bishop, CTO, Deca TechnologiesAdvanced IC Package Design Using Smart Pin Regions
Chris Cone, Senior Technical Marketing Engineer, Siemens EDADeveloping Low Cost Chiplet Packages
Nokibul Islam, Director Group Technology Strategy, JCET GroupCost Analysis of Chiplet Packaging Methods
Amy Lujan, VP Business Development, Savansys Solutions | Session Description:
| The days of simply selecting a chip package from a few common alternatives are over. Designers using chiplets must integrate package design with chip design and integration. They must have tools that consider packaging throughout the design process, so they can optimize cost, throughput, and heat and power factors over all stages. The goal is a one-stop shop providing heterogeneous integration that will drive faster time-to-market. Packaging can be a major way to add value to the ultimate product and meet the needs of system-level users.
| | About the Organizer/Moderator: | Atom Watanabe is a Research Staff Member at the IBM TJ Watson Research Center, where he works on IC packaging, 5G and millimeter-wave systems, RF electronics, and antenna design. His current research interests and expertise include high-frequency packaging, signal and power integrity analysis, and emerging approaches for multi-chiplet heterogeneous integration. He has over 40 publications in such journals as Applied Physics Letters, IEEE Transactions on Electromagnetic Compatibility, IEEE Transaction on Components, Packaging, and Manufacturing Technology, and IEEE Transactions on Microwave Theory and Techniques, and at such conferences as Electronic Components and Technology Conference (ECTC) and the International Symposium on Microelectronics. Dr. Watanabe has also received several paper awards. He earned a PhD in electrical and computer engineering from the Georgia Institute of Technology.
Laura Mirkarimi is VP 3D Technologies at Adeia, where she works on design, reliability engineering, and optimization analysis of package technologies. She was previously a Principal Scientist at Agilent Technologies. Regarded as one of the originators of hybrid bonding, she holds 70 patents. She also has over 50 publications including conference papers at ECTC, IWLPC, and ISTFA. She earned a PhD in materials science and engineering from Northwestern University.
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Tuesday, February 6th
8:30 AM-12:00 PM | | Pre-Conference Tutorial D: Interfaces (Section 1) (Pre-Conference Tutorials Track) | | Organizer: James Wong, CTO, Palo Alto Electron | Paper Presenters:
| BoW in Commercial Chiplet Designs Today - Click for Proceedings:
Elad Alon, CEO, Blue Cheetah Analog DesignFlexible eFPGA Based Demonstration Platform for Die-to-Die Interface Testing - Click for Proceedings:
Nick Ilyadis, VP Product Planning, AchronixAndy Heinig,
Head Efficient Electronics,
Fraunhofer IIS
UCIe: A Progress Report for 2024 - Click for Proceedings:
Gerald Pasdast, Sr Principal Engineer, IntelEfficient Monitoring, Test, and Repair of UCIe Links for Multi-Die Systems - Click for Proceedings:
Yervant Zorian, Chief Architect/Fellow, SynopsysSandeep Goel,
Academician/Director,
TSMC
Using Silicon Photonics in Co-Packaged Optical Interconnect - Click for Proceedings:
Manish Mehta, VP of Marketing and Operations, Optical Systems Division, Broadcom | Session Description:
| Fast on-chip die-to-die interfaces are the key to making the chiplet idea work. High data rates are essential for top performance and low latency. The interfaces also must consume little chip area or power or affect thermal budgets. Example buses such as Bunch-of-Wires (BoW) and Universal Chiplet Interface Express (UCIe) are already widely available. Designers must consider cost, chip area, throughput, and support when deciding which to use for their applications. The interface must be flexible, comprehensive, and easy to integrate with a wide variety of chiplets. Test and monitoring tools and platforms are particularly important in reducing time-to-market. Super-high performance applications, such as AI clusters, may require optical connections as well as electrical.
| | About the Organizer/Moderator: | James Wong is CTO at startup Palo Alto Electron, where he develops high-performance chiplets and chiplet design tools. He previously worked at zGlue, Oracle, Cisco, and Intel. James has made significant contributions to chiplet design and standardization projects such as the OCP CDXML, OCP chiplet models/integration workflow, and JEDEC JEP 30. He holds dual master's degrees in Computer Science and Electrical Engineering from the University of Michigan and the National University of Singapore, and has authored several influential industry publications.
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Tuesday, February 6th
8:30-12:00 PM | | Tutorial D Panel: Choosing the Right Die-to-Die Interface for Your Application (Pre-Conference Tutorials Track) | | Moderator: David McIntyre, Director Product Planning, Samsung Semiconductor | Panel Members:
| Panelist: Letizia Giuliano, VP IP Product Marketing/Management, Alphawave SemiPanelist: Mick Posner, VP HPC Interfaces, SynopsysPanelist: Elad Alon, CEO, Blue Cheetah Analog DesignPanelist: Frank Schirrmeister, CEO, Arteris IPPanelist: Kevin Donnelly, VP Strategic Marketing, Eliyan | Session Description:
| Fast on-chip die-to-die interfaces are the key to making the chiplet idea work. High data rates are essential for top performance and low latency. The interfaces also must consume little chip area or power or affect thermal budgets. Example buses such as Bunch-of-Wires (BoW) and Universal Chiplet Interface Express (UCIe) are already widely available. Designers must consider cost, chip area, throughput, and support when deciding which to use for their applications. The interface must be flexible, comprehensive, and easy to integrate with a wide variety of chiplets. Test and monitoring tools and platforms are particularly important in reducing time-to-market. Super-high performance applications, such as AI clusters, may require optical connections as well as electrical.
| | About the Organizer/Moderator: | David McIntyre is Director Product Planning at Samsung Semiconductor, where he leads product planning and business enablement for computational storage. He focuses on data center cloud to edge acceleration solutions in data analytics, security, and AI. He has been a program participant at the Persistent Memory Summit, Flash Memory Summit, and other forums. Before joining Samsung, he worked at Xilinx on new data center initiatives including blockchain. He has also worked at Intel and Altera where he focused on storage, test, and measurement applications for FPGAs. He earned an MSEE from Ohio University and an MBA from San Jose State University.
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Tuesday, February 6th
1:00-5:00 PM | | Pre-Conference Tutorial E: Design Methods (Pre-Conference Tutorials Track) | | Moderator: Tom Strothmann, VP North American Sales, BESIOrganizer: Jim Finnegan, COO, Netronome | Paper Presenters:
| Accelerating I/O Hub and Memory Chiplet Design
Erez Shaizaf, CTO, AlchipManmeet Walia,
Product Management Director,
Synopsys
New 3D IC Design Kits Cover Both Design and Packaging - Click for Proceedings:
Jawad Nasrullah, CEO, Palo Alto ElectronAnthony Mastroianni,
,
Physical-Aware Architecture Optimization for Multi-Die Systems
Holger Keding, Sr Staff R&D Engineer, SynopsysTaking Advantage of Chiplets in Today's Chip Designs - Click for Proceedings:
Bob Patti, President, nHanced Semiconductors | Session Description:
| Designing a chiplet is much like any other IC design, since the designer must balance among the usual power, performance, and area (PPA). However, new issues arise since the chiplet must fit into the overall chip design, so the designer must consider die-to-die interfaces and system-level problems. The interfaces must offer high bandwidth without using much chip area or power. Furthermore, the designer must make the chiplet be a useful citizen. It should serve a general purpose so it can fit into a range of designs and interface neatly with all of them. As chiplets become commonplace, many people will design them for sale or inclusion in libraries.
| | About the Organizer/Moderator: | Tom Strothmann is VP at Besi North America, where he manages North American operations and promotes advanced packaging equipment. He is a semiconductor packaging expert with extensive experience in flip-chip bumping, wafer-level chipscale packaging, fan-out technologies, and advanced packaging. Before joining Besi, he worked at K&S, STATS ChipPac, and FlipChip International. He has been active at many conferences, including being a keynoter at IMAPS ChipCon and a presenter at ECTC, 3DASIP, and IWLPC.
Jim Finnegan is COO at Netronome, a maker of network processors and SmartNICs. Before joining Netronome, he worked at Intel, where he was general manager of both the Network Processor Division and the Communication Infrastructure Group's Technology Office. He has over 30 years' experience in the networks and communications businesses, including positions at Digital Equipment and Tellabs. He earned Bachelor's and Master's degrees in electronic engineering from Queen's University Belfast (Northern Ireland).
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Tuesday, February 6th
1:00-5:00 PM | | Pre-Conference Tutorial F: Working with Foundries (Pre-Conference Tutorials Track) | | Moderator: Jean Bozman, President, Cloud ArchitectsOrganizer: Kenneth Larsen, Director Product Marketing, Synopsys | Paper Presenters:
| Intel Ponte Vecchio: The Soul of a New Chiplet-Based Processor - Click for Proceedings:
Pam Fulton, Principal Engineer, IntelWorking with New 3D IC Design Standards
Kenneth Larsen, Director Product Marketing, Synopsys3DFabric: Advanced Packaging Technologies and Design Ecosystem Collaboration" - Click for Proceedings:
Lluis Paris, Sr Director 3DFabric Alliance, TSMCEnsuring Yield and Reliability for Chiplets in a 3DIC Assembly - Click for Proceedings:
John Ferguson, Principal Engineer, Siemens EDA | Session Description:
| Developing chiplet-based multi-die systems requires major coordination between design team and foundry. The approach is new to both sides, and involves many new technologies, standards, and methods. In particular, designers must decide on the package early in the entire process since it will determine how the foundry approaches the problem. Chip and package designers will thus need to work together right from the beginning to achieve a successful integration. In practice, leading foundries have their own packaging services and standards. They play an important role in streamlining multi-die system designs driving early architecture, design implementation, manufacturing, and package integration. Obviously, there will be many more process decks for the customer to handle, and much more data to be managed. Overall, designers can expect to spend far more time working with the foundry than they did when designing monolithic chips.
| | About the Organizer/Moderator: | Jean Bozman is President/Principal Analyst at Cloud Architects, a research and consulting firm focused on cloud infrastructure. She is an expert industry analyst with over 20 years experience focused on the worldwide IT markets for databases, servers, storage, and software. Her primary focus is analyzing the technologies and market opportunities for data center infrastructure, including both clouds and enterprises. She is well-known from her long stint as IDC’s Research VP and primary analyst on servers. She is a frequent participant at conferences such as Flash Memory Summit and is often quoted in the trade and technical press, including BusinessWeek, Investor’s Business Daily, Bloomberg, and Reuters. She earned an MA from Stanford University.
Kenneth Larsen is Director Product Management at Synopsys, where he works on the 3DIC compiler platform, 3D heterogeneous integration, and advanced packaging. Before joining Synopsys, he worked at Mentor Graphics on technical sales of complex solutions and global field application engineering management He has 22 published articles in such media as Semiconductor Engineering and SemiWiki. He has worked with several trade and standards organizations, including being chair of Accellera and the VSI Alliance. He has presented at MEPTEC’s Road to Chiplets: Design Integration and Chiplet Summit.
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Tuesday, February 6th
1:00-5:00 PM | | Pre-Conference Tutorial G: AI in Chiplet Design (Pre-Conference Tutorials Track) | | Moderator: Rajesh Pendurkar, , TriSquare SenseOrganizer: Norman Chang, Chief Technologist, Electronics, Semiconductor, and Optics BU, Ansys, Inc., Ansys | Paper Presenters:
| How AI Can Help with Advanced Semiconductor Package Design - Click for Proceedings:
Keith Felton, Product Marketing Manager, Siemens EDAUsing ML in Simulation Tools for Chiplet-Based Design - Click for Proceedings:
Norman Chang, Chief Technologist, Electronics, Semiconductor, and Optics BU, Ansys, Inc., AnsysChipNeMo: Domain-Adapted LLMs for Chip Design - Click for Proceedings:
Mark Ren, Director of Design Automation Research, NVIDIAUsing AI in Federated Simulation for Chiplet-Based Design - Click for Proceedings:
Kevin Cameron, Consultant, Cameron EDA | Session Description:
| Chiplet-based design adds multiple chiplets and interfaces to systems already having millions of parameters, regions, and connections. AI/ML can help handle the increased complexity much as it has in many other areas. Typical uses include parameter value and consistency checks, rapid identification of problem areas, trend analysis, optimization procedures, and rule and standards checking. ML can simplify procedures, offer suggestions, explain error warnings, and make complex programs easier to use. Design tools can also offer interfaces to custom ML applications and to popular systems such as ChatGPT®. ML can even provide intelligent help with difficult tasks such as simulation and cooptimization.
| | About the Organizer/Moderator: | Rajesh Pendurkar is the founder of TriSquare Sense, a product development and engineering firm focused on ASIC design and test. He is also currently Engineering Director at Capgemini Engineering and has also held management and engineering positions at Intel, Broadcom, and Sun Microsystems. He is an Adjunct Faculty member at UC Santa Cruz. He has over 20 publications in such journals as IEEE Transactions on Computer-Aided Design of Integrated Circuits and at conferences such as International Test Conference (ITC). He holds six patents and is a member of the IEEE 1687 test technology standards committee workgroup. He earned a PhD in electrical and computer engineering at Georgia Tech.
Norman Chang is Fellow/Chief Technologist at Ansys, where he currently leads AI/ML and security initiatives. Before joining Ansys, he was Co-Founder/VP at Apache Design Solutions, a leading provider of innovative power analysis and optimization solutions. He also led a research group on power/signal/thermal integrity of chipsets based on VLIW architecture at HP Labs. He holds 25 patents and has co-authored over 60 papers and a popular book on “Interconnect Analysis and Synthesis” by Wiley-Interscience. He is an IEEE fellow and an active committee member at such major conferences as IEEE EDPS (Electronic Design Process Symposium). He earned a PhD in electrical engineering and computer science from UC Berkeley.
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Tuesday, February 6th
1:00-5:00 PM | | Pre-Conference Tutorial H: The New Open Chiplet Economy (Pre-Conference Tutorials Track) | | Organizer + Moderator: Cliff Grossner, Chief Innovation Officer, Open Compute Project (OCP)Organizer: Bapi Vinnakota, System Architect, Broadcom | Paper Presenters:
| Part 1 - Introduction: Progress in the Emerging Chiplet Economy
Bapi Vinnakota, System Architect, BroadcomPart 2 - Tools for the Open Chiplet Economy
Shahab Ardalan, VP Engineering, EnosemiLetizia Giuliano,
VP IP Product Marketing/Management,
Alphawave Semi
Part 3 - Open Chiplet Economy for AI and Edge
Jayaprakash Balachandran, Signal Integrity Engineer, d-MatrixTrent Uehling,
Technical Director,
NXP Semiconductors
Madhumita Sanyal,
,
Synopsys
Part 4 – Standardizing Chiplet Platforms
George Michelogiannakis, Research Scientist, LBNLBart Plackle,
VP Automotive,
imec
Andy Heinig,
,
Fraunhofer IIS
| Session Description:
| Chiplets have rapidly become the accepted way to develop chips at leading-edge nodes. In theory, they allow designers to drop known-good dies into their designs wherever needed. However, in practice, designers must have a way to quickly find what they want in a form they can use. A new chiplet economy is thus necessary. The Open Compute Project (OCP) has taken the lead in creating that economy. It started by supporting the Open Domain Specific Project (ODSA) in 2019, and it launched the "open chiplet economy" vision in 2023. The vision is quickly becoming reality. Its initial focus was on simplifying the definition of chiplet-based products by providing: 1. Business and technical workflows needed to assemble a chiplet-based product 2. Standards for creating IP for die-to-die interfaces 3. Reference tools for specifying, building, interfacing, inserting, and testing chiplets Remarkable progress has occurred since the launch. OCP and JEDEC have used an XML-based schema (developed by OCP) to create the JEP 30 standard. It allows EDA tools from multiple vendors to handle chiplets. Recently, 11 organizations showed real products and prototypes based on the standard. This puts the industry well on the way to defining interoperable chiplets that designers can easily use in applications. Current work emphasizes making chiplet-based products easier to develop and market. The community is creating standard form factors, developing supply chains, and creating an easily accessed marketplace. The idea is to help smaller or peripheral companies create chiplets for AI, IoT, HPC, financial, industrial and process control, and mil/aero markets that have low volumes. We also plan to join with marketing, sales, and business development specialists to identify what is needed to make chiplets financially viable.
| | About the Organizer/Moderator: | Cliff Grossner is Chief Innovation Officer at OCP where he leads its market intelligence and drives new programs including guiding inventors in developing early-stage company ideas, setting strategic direction and building awareness of OCP, establishing new alliances, and launching new activities. Before joining OCP, he headed the Cloud and Data Research Practice at Informa Tech, where he worked on cloud services, data center compute and networking, and data center infrastructure. He previously held senior positions at Alcatel-Lucent, Bell Labs, and Nortel. He earned his PhD at McGill University (Canada) and holds over 10 patents in networking and telecommunications.
Bapi Vinnakota leads the Open Domain-Specific Architecture (ODSA) sub-project within the Open Compute Project (OCP). At OCP, he works on the open chiplet economy, including the Bunch of Wires (BoW) die-to-die interconnect. He previously was an engineering manager at Broadcom, Netronome, and Intel. He is a long-time leader in open communities. He has several publications on ODSA and BoW, including an invited talk at the ACM/IEEE International Workshop on System-Level Interconnect Pathfinding (SLIP), presentations at Hot Interconnects, and an article in IEEE Micro. He earned a PhD in computer engineering from Princeton University.
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Tuesday, February 6th
1:00-5:00 PM | | Tutorial H Panel: Making the Open Chiplet Economy Grow (Pre-Conference Tutorials Track) | | Moderator: Dharmesh Jani, Open Source Ecosystem Leader, Meta | Panel Members:
| Panelist: Elad Alon, CEO, Blue Cheetah Analog DesignPanelist: Tom Hackenberg, Principal Analyst, Yole GroupPanelist: Letizia Giuliano, VP IP Product Marketing/Management, Alphawave SemiPanelist: Keith Nellis, , d-Matrix | Session Description:
| Chiplets have rapidly become the accepted way to develop chips at leading-edge nodes. In theory, they allow designers to drop known-good dies into their designs wherever needed. However, in practice, designers must have a way to quickly find what they want in a form they can use. A new chiplet economy is thus necessary. The Open Compute Project (OCP) has taken the lead in creating that economy. It started by supporting the Open Domain Specific Project (ODSA) in 2019, and it launched the "open chiplet economy" vision in 2023. The vision is quickly becoming reality. Its initial focus was on simplifying the definition of chiplet-based products by providing: 1. Business and technical workflows needed to assemble a chiplet-based product 2. Standards for creating IP for die-to-die interfaces 3. Reference tools for specifying, building, interfacing, inserting, and testing chiplets Remarkable progress has occurred since the launch. OCP and JEDEC have used an XML-based schema (developed by OCP) to create the JEP 30 standard. It allows EDA tools from multiple vendors to handle chiplets. Recently, 11 organizations showed real products and prototypes based on the standard. This puts the industry well on the way to defining interoperable chiplets that designers can easily use in applications. Current work emphasizes making chiplet-based products easier to develop and market. The community is creating standard form factors, developing supply chains, and creating an easily accessed marketplace. The idea is to help smaller or peripheral companies create chiplets for AI, IoT, HPC, financial, industrial and process control, and mil/aero markets that have low volumes. We also plan to join with marketing, sales, and business development specialists to identify what is needed to make chiplets financially viable.
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Tuesday, February 6th
5:00-6:00 PM | | Superpanel: How Can Chiplets Accelerate Generative AI Applications? (Panel Track) | | Session Sponsor: Achronix | | Organizer: Paul Borrill, Chief Product Officer, DaedaelusOrganizer: Rohit Mittal, Systems/Silicon Lead, GoogleModerator: Bill Wong, Technology Editor, Electronic Design | Panel Members:
| Panelist: Nick Ilyadis, VP Product Planning, AchronixPanelist: Durgesh Srivastava, Sr Director Hardware Engineering, NVIDIAPanelist: Rohit Mittal, Systems/Silicon Lead, GooglePanelist: Paul Fahey, VP Technology, SK hynixPanelist: Kevin Chen, Head/Partner Lam Capital, Lam ResearchPanelist: Paul Borrill, Chief Product Officer, Daedaelus | Session Description:
| Generative AI is the biggest topic in computer technology today. Everyone is talking about ChatGPT, its originator OpenAI, and its top executive Sam Altman. So what role can chiplets play as applications roll out in areas ranging from accounting through zoology? Surely chiplets can provide faster, more powerful AI chips, as well as devices that can bring generative AI to the edge. Also the chiplet form can be the way to add generative AI accelerators to processor designs. Still other applications include high-speed memory and I/O devices sitting close to processors inside packages to allow more in-memory computation and fewer data moves.
| | About the Organizer/Moderator: | Paul Borrill is founder and Chief Product Officer of Daedaelus and a leading industry expert on resilient network and storage infrastructures. He has been a major contributor to modern infrastructure development at such technology-leading companies and organizations as NASA, Apple, Sun Microsystems, and Quantum. Paul was cofounder of the Hot Interconnects conference and founding chair of the Storage Networking Industry Association (SNIA). Paul was also VP Technical Activities and VP Standards for the IEEE Computer Society, the leading worldwide technical society for computer engineering. Paul earned a PhD in Physics from University College London. He has presented at many conferences on distributed systems and holds nine patents in that area.
Rohit Mittal is Systems and Silicon Lead at Google, where he works on the tensor processing units (TPUs) that power AI services in Google Cloud and Google Infrastructure. Before joining Google, he was director in Intel’s Cloud and Data Center Products Groups. Rohit also founded two companies and worked in engineering at Ciena and Marvell. He has moderated/presented at many conferences including OCP. He earned an MSEE at Carnegie-Mellon University.
Bill Wong is Editor of Electronic Design Magazine, as well as Senior Content Director of its parent organization, Endeavor Business Media. One of the best-known editors in the technical press, he is noted for his interviews, analysis, and project articles. He focuses on embedded, software, and systems applications in the magazine. He has solid technical credentials, having earned a BSEE at Georgia Tech and an MSCS at Rutgers. He still works on hardware and software projects, including C, C++, and PHP programming and hardware ranging from robotics to AI systems.
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Tuesday, February 6th
6:00-8:30 PM | | Chat with the Experts (sponsored by Bolt Graphics) (Pre-Conference Tutorials Track) | | Expert Table Leaders:
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| The session allows attendees to meet top experts in many crucial areas and ask questions in an informal setting. Each table has a different subject, and attendees are welcome to move from table to table. Beer, wine, soft drinks, and pizza are served to promote the informal atmosphere and encourage networking. Emphasis is on frequently asked questions, best practices, hints and warnings, major issues, and key products and standards.
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