| Thursday, January 26th |
Thursday, January 26th
09:00-10:00 AM | | A-201: Interfaces (Design/Packaging/Interfaces/Applications Track) | | Moderator: Marc Hutner, Sr Director Product Marketing, proteanTecs | Paper Presenters:
| Creating a Sound Die-to-Die Interface for Today's Chiplet-Based Designs - Click for Proceedings:
Letizia Giuliano, VP Solution Engineering, Alphawave SEMIPerformance and Reliability Monitoring of Die-to-Die Interfaces - Click for Proceedings:
Nir Sever, Sr. Director, Business Development at proteanTecs, proteanTecsUCIe: An Open Standard Interface for Chiplet-Based Multi-Die Systems - Click for Proceedings:
Manuel Mota, Sr Staff Product Marketing Manager, SynopsysSimplifying Chiplet Interconnect Development with Interface IP
Manmeet Walia, Director Product Marketing, Synopsys | Session Description:
| The interface connecting chiplets is critical to chiplet-based design. It must be extremely fast, highly reliable, and very flexible. It must also be low-power and take little chip area. There are two major contenders: Universal Chiplet Interface Express (UCIe) from the UCIe Consortium and Bunch-of-Wires (BoW) from the Open Compute Project Foundation. Designers must determine which fits best in their applications, and which is most likely to develop a large support ecosystem.
| | About the Organizer/Moderator: | Marc Hutner is Sr Director of Product Marketing at proteanTecs, a leading start-up working on monitoring the health and performance of silicon and systems from design through field use. He works with customers, development teams, and executive management to define product requirements and understand product markets. Before joining proteanTecs, he had a long career at Teradyne, where he was Director Teradyne Canada and ATE system architect. A recognized industry expert in design, design-for-test, and testing, he has presented at many events including Linley Fall Processor Conference, VLSI Test Symposium, International Test Conference, and SEMICON West. He has also been a member of industry councils including the Test Technology Working Group, Heterogeneous Integration Roadmap Leadership Team. He earned a Bachelor of Computer Engineering from McGill University (Canada) and an MS in Engineering Management from Tufts University.
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Thursday, January 26th
09:00-10:00 AM | | B-201: Partitioning (Disaggregation) (Partitioning/Integration/Test Track) | | Moderator: Paul Franzon, Professor, North Carolina State University | Paper Presenters:
| Guidelines for Designing Chiplet-Based Processors
, , Chiplet Partitioning Can Balance Among Performance, Flexibility, and Scalability - Click for Proceedings:
Denis Dutoit, Sr Project Coordinator, CEA-List | Session Description:
| Partitioning (or disaggregation) is a completely new development stage introduced by chiplet-based design. Chip designers must determine how to divide the chip area into chiplets, which may be new designs, old designs (presumably at older process nodes), third-party IP, or derived from other sources (such as a chiplet market). The decisions are difficult to make and depend on many factors, such as cost, power, availability and compatibility of chiplets, limitations of design tools, and designer experience. Partitioning obviously has a critical effect on the remaining design process, including the ability to balance among performance, flexibility, and scalability.
| | About the Organizer/Moderator: | Paul Franzon is a professor and Director of Graduate Programs at North Carolina State University (NCSU). He is also the Site Director Center for Advanced Electronics through Machine Learning (CAEML). A well-known researcher, he has over 400 published papers in such journals as IEEE Transactions on VLSI Systems, IEEE Transactions on Circuits and Systems, and IEEE Electron Device Letters and at important conferences such as ECTC, 3DIC, IEDM, ICCAD, EPEPS, and SOCC. He has also written books and contributed chapters to them. Before joining the NCSU faculty, he worked at AT&T Bell Laboratories and Australia Telecom. He has also founded four technology companies. He earned a PhD from the University of Adelaide (Adelaide, Australia). He is an IEEE Fellow and has received many research and teaching awards.
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Thursday, January 26th
09:00-10:00 AM | | C-201: Best Packaging for Chiplets Today Panel (sponsored by ASE) (Panel Track) | | Organizer + Moderator: Nokibul Islam, Sr Director Field Application Engineering, JCET Group | Panel Members:
| Panelist: Daniel Lambalot, Sr Principal Engineer, Alphawave SemiPanelist: Laura Mirkarimi, VP 3D Technologies, AdeiaPanelist: Syrus Ziai, VP Engineering, EliyanPanelist: Dick Otte, CEO, Promex IndustriesPanelist: Mike Kelly, VP Advanced Packaging Technology Integration, Amkor Technology | Session Description:
| Packaging is one of the most difficult areas for chiplet designers. Packages must be capable of handling power and heat dissipation, be reasonably priced and small, and be rugged enough for standard applications. Issues of concern include who selects the package and how, which packages are best-suited to chiplet-based designs, what breakthroughs we can expect in packaging over the next few years, and what are the best tradeoffs among size, performance, features, and cost for the many types of packages available today.
| | About the Organizer/Moderator: | Nokibul Islam is Sr Director Field Applications Engineering at JCET Group, where he focuses on semiconductor packaging technology, product development, qualification, product management, and marketing. Before joining JCET Group, he was an engineer at Amkor. He has published many papers on electronic packaging design and has presented at many conferences including IMAPS, ECTC, and DPC. He has been a program committee member for many conferences and is the General Chair for the 19th Annual Device Packaging Conference (DPC 2023). He earned a PhD in mechanical engineering from Auburn University (AL).
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Thursday, January 26th
09:00-10:00 AM | | D-201: Annual Update on Test of Multi-Die Designs (Annual Update Track) | | Moderator: Soheil Modirzadeh, Strategic Communications Manager, Synopsys | Paper Presenters:
| Annual Update on Test of Multi-Die Designs
Mike Ricchetti, SoC/DFT Architect, SynopsysYervant Zorian,
Chief Architect/Fellow,
Synopsys
| Session Description:
| Advances in chiplet test involve the development of benchmarks, test procedures, and analysis packages. Other requirements include interoperability testing for interfaces, standards for thermal and power analysis, and the evolution of new ways to provide basic power, clocking, and other functions to an entire aggregate of chiplets. Test is a key issue because it can easily exceed time and cost estimates due to the need for both chiplet and package-level testing.
| | About the Organizer/Moderator: | Soheil Modirzadeh is Sr Staff Strategic Communications at Synopsys, where he collaborates with technical teams to create quality marketing content. He emphasizes product differentiation and value propositions. He has over 25 years experience in technical marketing, including stints with Cadence and Xilinx before joining Synopsys. He earned an MBA from the University of Phoenix and a BSBA from San Jose State University. He has chaired industry events such as MIPI Devcon in India, Taiwan, and Korea.
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Thursday, January 26th
02:00-3:20 PM | | A-202: Packaging - 2 (Design/Packaging/Interfaces/Applications Track) | | Moderator: Larry Zu, President, Sarcina Technology | Paper Presenters:
| Warpage Simulation for Assessing Chip-Package Interaction in 3D Stacks - Click for Proceedings:
Junho Choy, Engineer, Siemens EDASuccessful Implementation of Chiplet-Based Heterogeneous Advanced Packages - Click for Proceedings:
Keith Felton, Product Marketing Manager, Siemens EDA | Session Description:
| Packaging chiplets involves many new issues that designers must understand. They include flip chip mass reflow, thermocompression bonding and microbumps, die to wafer hybrid bonding, die stacking, filter die bonding, and bridge die attach. Gone are the old days when there were just a few package choices. Furthermore, the new 3D approach adds complications due to chip-package interaction. The solution is for designers to start thinking about packages early in the overall process to produce a result that has the needed performance at the right price.
| | About the Organizer/Moderator: | Larry Zu is the founder/CEO of Sarcina Technology, where he designs advanced semiconductor packages to achieve first tape-out success through rigorous chip-package-board co-design and co-simulation. He also specializes in product engineering for wafer and assembly yield enhancement, Q&R, and supply chain management. Before founding Sarcina Technology, he worked on processor projects at Bell Labs, DEC, Intel, and TSMC. He has taped out almost 1,000 packages with an over 99% first-time tape-our success rate. He earned a PhD in electrical engineering from Rutgers University (NJ). He has many refereed IEEE publications and holds multiple patents used in leading US companies’ key products.
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Thursday, January 26th
02:00-3:20 PM | | B-202: How to Make Chiplets a Viable Market (Panel) (Panel Track) | | Organizer + Moderator: Ravi Agarwal, Technical Sourcing Manager, Meta | Panel Members:
| Panelist: Durgesh Srivastava, Sr Director, NVIDIAPanelist: Clint Walker, VP Marketing, Alphawave SEMIPanelist: Mark Kuemerle, VP/CTO ASIC Business Unit, MarvellPanelist: Travis Lanier, VP Marketing, Ventana Micro SystemsPanelist: Kevin Yee, Director IP Marketing, Samsung Semiconductor | Session Description:
| Many articles have discussed how chiplet-based design could become a drop-in business in which designers select the chiplets they want from a marketplace. Obviously, such a concept depends on a viable market in which chiplet designers could make a reasonable return on their investment. Clearly there would have to be standards for chiplets so chip designers would know what they’re getting and how it would integrate into their devices. The chiplet would need to have a specification sheet lists its connections and its characteristics in a specific manner. The chiplet would also have to pass both security and interoperability tests. Clearly such a marketplace will take time to develop and will require an organization to oversee it.
| | About the Organizer/Moderator: | Ravi Agarwal is a Technical Sourcing Manager at Meta, where he focuses on chiplet strategy, advanced packaging architecture, supply chain, strategic sourcing, and open ecosystem development. He also is the Chair of the IEEE Electronic Packaging Society’s Silicon Valley chapter and the Lead of the ODSA Chiplet Business Working Group. He was previously Director of Strategy and Chief of Staff for a Corporate VP at Intel and Director of Product Management at Amkor. He earned a PhD in Materials Science and Engineering at North Carolina State University and an MBA from UC Berkeley. He has 14 published papers and holds three patents.
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Thursday, January 26th
02:00-3:20 PM | | C-202: Highlights from University Research on Chiplets (Academic Track) | | Moderator: Paul Borrill, CEO, Daedaelus | Paper Presenters:
| Designing a 2000 Chiplet Waferscale Processor - Click for Proceedings:
Puneet Gupta, Professor, UCLAA New Heterogeneous Chiplet-Based Architecture for AI Computing - Click for Proceedings:
Yu Cao, Professor, Arizona State UniversityAI Chiplet Set for Inference and Training with Supply Chain Security - Click for Proceedings:
Paul Franzon, Professor, North Carolina State UniversityChiplet-Based Image Processor for Wide-Area Surveillance
Andreas Andreou, Professor, Johns Hopkins University | Session Description:
| Academic research in chiplets has progressed rapidly in the past few years and provides great insight into a rapidly expanding technical area. This session includes presentations on a new approach to creating chiplets for AI computing, the design of a waferscale processor involving almost 2,000 chiplets, and an AI chiplet set that includes supply chain security. All of them illustrate uses of chiplet design that could well become commercially important in the future.
| | About the Organizer/Moderator: | Paul Borrill is founder and Chief Product Officer of Daedaelus and a leading industry expert on resilient network and storage infrastructures. He has been a major contributor to modern infrastructure development at such technology-leading companies and organizations as NASA, Apple, Sun Microsystems, and Quantum. Paul was cofounder of the Hot Interconnects conference and founding chair of the Storage Networking Industry Association (SNIA). Paul was also VP Technical Activities and VP Standards for the IEEE Computer Society, the leading worldwide technical society for computer engineering. Paul earned a PhD in Physics from University College London. He has presented at many conferences on distributed systems and holds nine patents in that area.
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Thursday, January 26th
03:30-4:50 PM | | A-203: Design - 2 (Design/Packaging/Interfaces/Applications Track) | | Moderator: James Wong, CTO, Palo Alto Electron | Paper Presenters:
| Using AI to Speed up Power Analysis for Chiplet Based Designs
Kendall Hiles, Sr Product Specialist High Density Packaging, Siemens EDAInnovative Method for Automated Chiplet Assembly and Physical Verification
John Ferguson, Director Product Management, Siemens EDA | Session Description:
| Successful chiplet design depends heavily on two key approaches: automation and early prediction. Everything must be automated as much as possible to require little designer intervention. Most chips will be far too complex for manual methods to work. Early prediction allows designers to catch problems before they cause design delays. Achieving it may require intelligent interfaces that allow designers to use tools such as signal integrity, thermal, and power analysis that only specialists have employed in the past.
| | About the Organizer/Moderator: | James is currently CTO at Palo Alto Electron, a startup developing tools for chiplet-based design. With over 20 years experience in software design automation, simulation, firmware, and hardware design, he has developed both intellectual property and patents for software and hardware applications. He is an active member of Open Compute Project (OCP) and Chiplet Design Exchange (CDX) for chiplet standardization. He is a co-author of the ZEF/CDXML chiplet exchange format. He led the engineering team to develop the popular open-source zGlue chiplet integration and EDA. He has previous experience as a Director, Manager, and Engineer at Ma Labs, Oracle, Cisco, and Intel. He earned a Masters degree in Electrical Engineering and Computer Science from the University of Michigan and National University of Singapore.
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Thursday, January 26th
03:30-4:50 PM | | B-203: Chiplets in 2028 and How We Got There (Panel) (Panel Track) | | Organizer + Moderator: Matthew Ouelette, Director Silicon Product Planning, AMD | Panel Members:
| Panelist: Tom Hackenberg, Principal Analyst, Yole IntelligencePanelist: John Shalf, Department Head, Lawrence Berkeley National LaboratoryPanelist: Jawad Nasrullah, CEO, Palo Alto ElectronPanelist: Omar Hassen, SVP Business Development, Ventana Micro SystemsPanelist: Bapi Vinnakota, ODSA Project Lead, Open Compute ProjectPanelist: Millind Mittal, VP Data Center Technologies, AMD | Session Description:
| The five-year horizon for chiplets is very promising. They will make up an ever increasing part of the large chip market, as their cost is more than balanced by the tremendous advantages they bring to chip design and development. More development platforms, operating systems, utilities, and other tools will be available for them. Standardization will be a major issue, as most large customers will want multiple sources as well as large ecosystems and wide support for both development and test. Other issues include achieving higher throughput and lower latency, isolating executing applications from one another, security, and EDA, packaging, integration, and test platform support.
| | About the Organizer/Moderator: | Matthew Ouellette is Director Silicon Product Planning at AMD, where he is responsible for product definition and high-level architecture of next-generation devices targeting a variety of applications, including AI/ML, wireless, SmartNICs, and automotive. His technical areas of special interest include AI/ML inference workloads, disaggregation through chiplets, and data center acceleration. He is responsible for silicon and package level specifications, competitive analysis, and market research. He has published several technical papers and presented at Hot Chips on AMD’s Versal Compute Acceleration Platform. Before joining AMD, he worked at Xilinx and Mercedes-Benz R&D, and has 10+ years developing applications on FPGA-based platforms. He earned a BSEE at the University of Maryland. He holds two US patents and three UK patents.
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