| Wednesday, January 25th |
Wednesday, January 25th
09:00-10:00 AM | | Chiplets: Where We Are Today (Plenary Track) | | Moderator: Chuck Sobey, General Chair, Chiplet Summit | Paper Presenters:
| Chiplets Market Update - Click for Proceedings:
Tom Hackenberg, Principal Analyst, Yole IntelligenceState of Chiplets Today - Click for Proceedings:
Jawad Nasrullah, CEO, Palo Alto Electron | Session Description:
|
| | About the Organizer/Moderator: | Chuck Sobey is General Chair of SmartNICs Summit. He leads a team of industry veterans to organize the Summit, identifying key trends, topics, and speakers. Chuck is a respected memory and storage technology strategist, researcher, and lecturer. As Chief Scientist of ChannelScience, he guides clients in evaluating emerging memory and storage technologies and maximizing their reliability and performance. He uses probability analysis to match a technology's projected capabilities to an application's requirements. His team has won SBIR awards from the US Department of Energy to advance the field of magnetic tape recording, on which practically all of the hyperscale and cloud services rely. Chuck is also the Conference Chair of Flash Memory Summit, which he helped lead to become the number one independent storage event. He earned an MS ECE from the University of California, Santa Barbara and a BS ECE from Carnegie Mellon University. He holds 7 US patents.
|
|
Wednesday, January 25th
02:00-3:00 PM | | A-101: Packaging - 1 (Design/Packaging/Interfaces/Applications Track) | | Moderator: Junho Choy, Engineer, Siemens EDA | Paper Presenters:
| Improving Electromagnetic Simulation for Chiplet-Based IC Designs - Click for Proceedings:
Feng Ling, CEO & Founder, XpeedicHandling Thermo-Mechanical Stress in Chiplets - Click for Proceedings:
John Wilson, Business Development Mgr, Siemens EDAImproved Process for Thin Glass Interposers
David Levy, Dir. R&D, Mosaic Mircosystems | Session Description:
| Packaging has become a major stage in chiplet-based design. It greatly affects both power analysis and the introduction of bases (such as interposers) for interconnections, power, clocking, and other system requirements. Interposers provide a good base on which to build chiplet-based systems, but silicon ones are expensive, hence the interest in cheaper alternatives such as glass. Silicon interposers also introduce effects of their own, such as thermo-mechanical stress due to stiffness, requiring extra analysis early in the design process to avoid problems requiring rework.
| | About the Organizer/Moderator: | Jun-Ho Choy is an R&D Engineer in the Design to Silicon Division of Siemens EDA. He previously worked at SK Hynix on process development to improve device reliability, and LSI Logic on development of an electromigration simulator. Choy earned a PhD in metallurgical and materials engineering from Michigan Technological University. He has published 26 articles in technical journals such as IEEE Transactions on Computer-Aided Design, Journal Vacuum Science and Technology, and the Journal of Electronic Packaging. He has also published conference presentations in such events as International Symposium on Physical Design (ISPD), International 3D Systems Integration Conference (3DIC), and the IEEE International Reliability Physics Symposium (IRPS).
|
|
Wednesday, January 25th
02:00-3:00 PM | | B-101: Integration - 1 (sponsored by EMD Electronics) (Partitioning/Integration/Test Track) | | Moderator: Milind Weling, Head Neuromorphic Realization, EMD Electronics | Paper Presenters:
| Using High-Performance FPGA Chiplets in Heterogenous Systems - Click for Proceedings:
Nick Ilyadis, Sr. Director of Product Planning, AchronixOptimizing Chiplets Using Heterogeneous Integration and Co-Optimization - Click for Proceedings:
Per Viklund, Director IC Packaging, Siemens EDADeveloping an FPGA Chiplet
Kash Johal, VP of Sales, eTopusMao Wang,
Director Product Marketing,
QuickLogic
| Session Description:
| Heterogeneous integration is surely the most difficult stage of chiplet development. It involves everything from ensuring that the chiplets actually fit in the package in the right order through power and thermal analysis. The designers must optimize everything together (so-called co-optimization) and manaqe to create a manufacturable device. The system-in-chip itself requires a controller to manage both control signals and data. One option is to use an FPGA chiplet to produce the needed signals. The FPGA approach offers flexibility and simplifies late changes, but also uses chip area and may consume a lot of power.
| | About the Organizer/Moderator: | Milind Weling is the Head of Neuromorphic Realization and co-founder of the Neuromorphic Computing incubator of EMD Electronics, a business of Merck KGaA Darmstadt Germany. Previously he led Customer Programs and Operations for Intermolecular, where he drove the discovery and optimization of new materials, integrated module solutions, and leading edge devices. Milind has extensive experience in advanced memory and logic technology development, DFM and design-process interactions, new product introduction, and foundry management. He previously held senior engineering and management positions at Cadence Design Systems, Sun Microsystems, Philips Semiconductors, and VLSI Technology. Milind earned an MSEE at the University of Hawaii. He holds 50+ patents and has co-authored over 70 technical papers, primarily focused on semiconductor process technology, device reliability, and integration.
|
|
Wednesday, January 25th
02:00-3:00 PM | | C-101: Overcoming Chiplet Design Challenges - How Industry Can Help (Panel) (Panel Track) | | Organizer: Sid Allman, Senior Director System/ASIC Architecture/Solutions, MarvellModerator: Jean Bozman, President/Chief Analyst, Cloud Architects | Panel Members:
| Panelist: Patrick Soheili, Co-Founder, EliyanPanelist: Rishi Chugh, VP Product Marketing, CadencePanelist: Luis Rodriguez, Senior Solutions Architect, Avery Design SystemsPanelist: Nir Sever, Sr. Director, Business Development at proteanTecs, proteanTecsPanelist: Mark Kuemerle, VP/CTO ASIC Business Unit, Marvell | Session Description:
| Chiplet designers face many challenges. Chiplets must be usable across a wide variety of applications, be optimized for power consumption and heat dissipation, satisfy standard PPA requirements, interface easily, and allow for varied processes and nodes. Industry can help by providing standards or guidelines for chiplet developers to follow, offering test suites and interoperability events, and complying with standards from JEDEC and other groups. A new organization to create and oversee the chiplet marketplace would be helpful as well.
| | About the Organizer/Moderator: |
Jean Bozman is President/Principal Analyst at Cloud Architects, a research and consulting firm focused on cloud infrastructure. She is an expert industry analyst with over 20 years of experience focused on the worldwide IT markets for databases, servers, storage, and software. Bozman’s primary focus is analyzing the technologies and market opportunities for data center infrastructure, including both cloud and enterprise data centers. By taking a holistic perspective on the combination of hardware and software, she analyzes workloads handled by on-premises and off-premises hybrid clouds. She also focuses on the impact on storage and the emerging market for Software Defined Infrastructure (SDI). She is well-known from her long stint as IDC’s Research VP and primary analyst on servers. She is a frequent participant at conferences such as Flash Memory Summit and is often quoted in the trade and technical press, including BusinessWeek, Investor’s Business Daily, Bloomberg, and Reuters. She earned an MA from Stanford University and has participated in graduate professional business programs at Stanford and UJC Berkeley.
|
|
Wednesday, January 25th
02:00-3:00 PM | | D-101: Annual Update on Packaging (Annual Update Track) | | Moderator: David McIntyre, Director Product Planning, Samsung Electronics | Paper Presenters:
| Annual Update on Packaging - Click for Proceedings:
Andy Heinig, Group Leader, Fraunhofer IIS | Session Description:
| Chiplet packaging depends on heterogeneous integration of multiple chiplets into a single chip. The package must support a variety of devices, based on different process nodes, substrates, and technologies. It must also provide sufficient heat flow to keep the chiplets from going outside normal operating levels. And it must allow for the interconnections and support mechanisms such as interposers needed to create a viable system. Today’s advanced packages increase system-level interconnection density, reduce power consumption, integrate more functions, lower cost, and achieve smaller size.
| | About the Organizer/Moderator: | David McIntyre is Director Product Planning at Samsung Semiconductor, where he leads product planning and business enablement for computational storage. He focuses on data center cloud to edge acceleration solutions in data analytics, security, and AI. He is also a member of the SNIA Computational Storage SIG and a program participant at the Persistent Memory Summit, Flash Memory Summit, and other forums. Before joining Samsung, he worked at Xilinx where he handled new data center initiatives including blockchain. He has also worked at Intel and Altera where he focused on storage, test, and measurement applications for FPGAs. He earned an MSEE from Ohio University and an MBA from San Jose State University.
|
|
Wednesday, January 25th
03:15-4:15 PM | | A-102: Applications (Design/Packaging/Interfaces/Applications Track) | | Moderator: Nokibul Islam, Sr Director Field Application Engineering, JCET Group | Paper Presenters:
| Dynamically Reconfigurable Chiplet Substructures Advance Distributed Computing
Paul Borrill, CEO, DaedaelusUsing Chiplets to Develop Advanced Driver Assistance Systems (ADAS) for Vehicles - Click for Proceedings:
Andy Heinig, Group Leader, Fraunhofer IISChiplet-Based Switch SoC for CXL Resource Pooling
Shreyas Shah, CTO, Elastics.cloud | Session Description:
| The chiplet approach can serve a wide range of applications. One popular example is driver-assistance systems for vehicles. Furthermore, the chiplet substructure may itself be dynamically reconfigurable to allow system changes for clouds where the mix of applications is constantly changing.
| | About the Organizer/Moderator: | Nokibul Islam is Sr Director Field Applications Engineering at JCET Group, where he focuses on semiconductor packaging technology, product development, qualification, product management, and marketing. Before joining JCET Group, he was an engineer at Amkor. He has published many papers on electronic packaging design and has presented at many conferences including IMAPS, ECTC, and DPC. He has been a program committee member for many conferences and is the General Chair for the 19th Annual Device Packaging Conference (DPC 2023). He earned a PhD in mechanical engineering from Auburn University (AL).
|
|
Wednesday, January 25th
03:15-4:15 PM | | B-102: Test (Partitioning/Integration/Test Track) | | Moderator: Denis Dutoit, Sr Project Coordinator, CEA-List | Paper Presenters:
| DFT Architecture for Chiplet-based Systems in Package - Click for Proceedings:
Rajesh Pendurkar, Director, CapgeminiMicro-Textured Film Aids in Universal Handling of 3D Devices
Raj Varma, CTO, Delphon/Gel-Pak | Session Description:
| Test generally consumes about half of the budget for developing a chip. And the chiplet approach may raise that percentage, since it requires extensive testing at both the chiplet and the system level. Chip developers must look for economies everywhere to reduce test costs, ranging from the handling of the devices to a DFT-based architecture that makes chips and chiplets easier to test.
| | About the Organizer/Moderator: | Denis Dutoit is a Senior Project Leader in Advanced Computing at CEA-List, one of the world's largest organizations for research in nanotechnology, microelectronics, architecture and system integration. He coordinated the European ExaNoDe project that developed a computer node demonstrator combining chiplets, an active interposer, and bare dies within a System-in-Package (SiP). He has also contributed to the architecture definition of the European Processor Initiative (EPI). His current focus is on architecture pathfinding into chiplet-based designs. Before joining CEA, he was a system-on-chip architect at ST Microelectronics and ST Ericsson. He earned a PhD in signal processing from Telecom Paris, France, in 1988. He has authored or coauthored over 20 articles, including invited talks and tutorials at IEEE-sponsored conferences.
|
|
Wednesday, January 25th
03:15-4:15 PM | | C-102: Best Way to Optimize Chiplets (Panel) (Panel Track) | | Moderator: Atom Watanabe, Research Staff Member, IBMOrganizer: Kenneth Larsen, Director Product Management, Synopsys | Panel Members:
| Panelist: Kenneth Larsen, Director Product Management, SynopsysPanelist: Jonathon Evans, Principal Architect, NVIDIAPanelist: Elad Alon, CEO & Co-founder, Blue Cheetah Analog DesignPanelist: Ramin Farjad, CEO, EliyanPanelist: Ken Chang, Corporate VP Design IP Engineering, Cadence | Session Description:
| Chiplet design faces many challenges. Chiplets must be usable across a wide variety of applications, be optimized for power consumption and heat dissipation, satisfy standard PPA requirements, interface easily, and allow for varied processes and nodes. Industry can help by providing standards or guidelines for chiplet developers to follow, offering test suites and interoperability events,and complying with standards from JEDEC and other groups.
| | About the Organizer/Moderator: | Atom Watanabe is a Research Staff Member at the IBM TJ Watson Research Center, where he works on IC packaging, 5G and millimeter-wave systems, RF electronics, and antenna design. His current research interests and expertise include high-frequency packaging, signal and power integrity analysis, and emerging approaches for multi-chiplet heterogeneous integration. He has over 40 publications in such journals as Applied Physics Letters, IEEE Transactions on Electromagnetic Compatibility, IEEE Transaction on Components, Packaging, and Manufacturing Technology, and IEEE Transactions on Microwave Theory and Techniques, and at such conferences as Electronic Components and Technology Conference (ECTC) and the International Symposium on Microelectronics. Dr. Watanabe has also received several paper awards. He earned a PhD in electrical and computer engineering from the Georgia Institute of Technology.
|
|
Wednesday, January 25th
03:15-4:15 PM | | D-102: Annual Update on Chiplet Design: Multi-Die System in the post Moore Era (Annual Update Track) | | Moderator: Soheil Modirzadeh, Strategic Communications Manager, Synopsys | Paper Presenters:
| Annual Update on Chiplet Design: Multi-Die System Design in the SysMoore Era
Shekhar Kapoor, Sr. Director of Product Marketing, Synopsys | Session Description:
| Chiplet design requires full integration with all stages of development from partitioning through packaging, test, integration, and manufacturing. The major new concept is the idea of creating a building block that can be simply dropped into other designs or even sold on the open market. So the design must emphasize generality and standards (including die-to-die interfaces). Of course, the usual IC design requirements for optimizing power, performance, and area (PPA) still apply.
| | About the Organizer/Moderator: | Soheil Modirzadeh is Sr Staff Strategic Communications at Synopsys, where he collaborates with technical teams to create quality marketing content. He emphasizes product differentiation and value propositions. He has over 25 years experience in technical marketing, including stints with Cadence and Xilinx before joining Synopsys. He earned an MBA from the University of Phoenix and a BSBA from San Jose State University. He has chaired industry events such as MIPI Devcon in India, Taiwan, and Korea.
|
|
Wednesday, January 25th
04:30-5:30 PM | | A-103: Design - 1 (Design/Packaging/Interfaces/Applications Track) | | Moderator: Gordon Allan, Product Manager, Siemens EDA | Paper Presenters:
| Bringing Persistent Memory to Chiplets - Click for Proceedings:
Bill Gervasi, Principal Systems Architect, NanteroEnergy-Centric AI Acceleration with Chiplet Based Design - Click for Proceedings:
Robert Beachler, VP Product, Untether AIManaging IP During Chiplet Design and Integration - Click for Proceedings:
Michael Munsey, Sr Director Semiconductor/IP Solutions, Siemens EDA | Session Description:
| Chiplet-based design requires many new and upgraded tools. The usual analysis and verification platform must be extended to handle multiple chiplets and data must be managed. All of this is complicated by the need to apply everything both to individual chiplets and to the package as a whole. Runtimes will lengthen for entire packages, and the number of runs obviously depends directly on the number of chiplets. Drop-in chiplets would help reduce the strain if methods can be developed for assuring their characteristics and performance.
| | About the Organizer/Moderator: | Gordon Allan is Product Manager for Verification IP at Siemens EDA, where he focuses on delivering advanced verification solutions for complex SoC designs. Gordon has had a long career as an SoC design and verification expert. He was a co-author of Accellera’s popular Universal Verification Methodology (UVM), and he published the widely used online UVM Cookbook on the Verification Academy website. Before joining the EDA industry, he spent over 18 years leading and developing SoC and complex protocol IP/VIP projects in semiconductor companies, fabless startups, EDA companies, and system houses. Gordon earned a BSc with honors in computer science from the University of the West of Scotland. He has published eight papers at such conferences as DVcon and ARM TechCon.
|
|
Wednesday, January 25th
04:30-5:30 PM | | B-103: Integration - 2 (Partitioning/Integration/Test Track) | | Moderator: Nathan Brookwood, Research Fellow, Insight 64 | Paper Presenters:
| Developing and Managing System Netlists for Chiplet Integration - Click for Proceedings:
Mike Walsh, Technical Director – IC Packaging Solutions, SiemensSimple, Low-Cost Method for Connecting Off-the-Shelf Chiplets - Click for Proceedings:
Ramin Farjadrad, CEO, EliyanUsing Predictive SI Analysis to Ensure Successful Chiplet Integration - Click for Proceedings:
Subramanian (Lal) Lalgudi, Analysis/Verification Product Specialist, Siemens EDA | Session Description:
| Chiplet-based integration is a complex process. Even the development and management of netlists is complicated by the need to handle connections between chiplets. And advanced packages are also more difficult to integrate than traditional simple ones. The development team must plan integration carefully to avoid having the task overrun the original schedule. A new approach to chiplet integration allows the connection of any chiplet via a PHY and an interface-to-interface converter.
| | About the Organizer/Moderator: | Nathan Brookwood is Research Fellow at Insight 64, a semiconductor consulting firm. He has focused recently on microprocessors used in computational applications. His views on the microprocessor market often find their way into articles in mainstream media, business media, and the trade press. He has worked for and with suppliers of mainframes, minicomputers, personal computers, and semiconductors, and he has analyzed and commented on the industry for D.H. Brown Associates and Dataquest. During his 40 year career in the industry, Mr. Brookwood has experience with Micronics Computers, Intergraph, Convergent Technologies, Prime Computer, and Digital Equipment. He is a graduate of MIT and has taken classes at Harvard Business School.
|
|
Wednesday, January 25th
04:30-5:30 PM | | C-103: Next Great Breakthrough in Chiplets (Panel) (Panel Track) | | Moderator: Dean Freeman, Chief Analyst, FTMAOrganizer: Jim Finnegan, Sr VP Engineering, Netronome | Panel Members:
| Panelist: Erez Shaizaf, CTO, AlchipPanelist: Robert Patti, President, nHanced SemiconductorsPanelist: Craig Bishop, CTO, DecaPanelist: Mike Li, VP Engineering/New Products, Corigine | Session Description:
| Many important changes will surely occur in the emerging chiplets arena. They may include new combined packages that allow designers to co-optimize chiplets from the partitioning stage through integration and test. Other possible advances could include standards that allow for portability of chiplets from one application to another, better test tools and interposers, interoperability testing, and exchanges or chiplet stores that allow designers to readily find the chiplets they need from a variety of sources.
| | About the Organizer/Moderator: | Dean Freeman is Chief Analyst at FTMA, where he specializes in semiconductor manufacturing and materials. He is also a contributor to InCites magazine on heterogeneous integration and the author of many articles. Before founding FTMA, he was a VP Market Research at Gartner, where he tracked semiconductor manufacturing, process technology, and the Internet of Things. He has also held industry positions with Watkins Johnson, Lam Research, and Texas Instruments where he had responsibility for every aspect of semiconductor manufacturing from wafer selection to the final product. He holds 9 process and equipment patents. He earned an MS in physical chemistry from University of Nevada Reno.
Dean Freeman is Chief Analyst at FTMA, where he specializes in semiconductor manufacturing and materials. He is also a contributor to InCites magazine on heterogeneous integration and the author of many articles. Before founding FTMA, he was a VP Market Research at Gartner, where he tracked semiconductor manufacturing, process technology, and the Internet of Things. He has also held industry positions with Watkins Johnson, Lam Research, and Texas Instruments where he had responsibility for every aspect of semiconductor manufacturing from wafer selection to the final product. He holds 9 process and equipment patents. He earned an MS in physical chemistry from University of Nevada Reno.
|
|
Wednesday, January 25th
04:30-5:30 PM | | D-103: Annual Update on Interfaces (Annual Update Track) | | Moderator: Anu Ramamurthy, Staff Engineer, Microchip | Paper Presenters:
| Annual Update on Interfaces - Click for Proceedings:
Mick Posner, Product Line Sr Group Director, Synopsys | Session Description:
| The common interfaces for chiplet design today are BoW (Bunch of Wires) from the Open Compute Project (OCP) and UCIe (Universal Chiplet Interface Express) from the UCIe Consortium. Both are open standards that support many architectures and have emerging ecosystems. Both have governing bodies that issue extensions and revisions and provide training, education, and other support.
| | About the Organizer/Moderator: | Anu Ramamurthy is a Sr Staff Engineer at Microchip Technology, where she works on heterogeneous integration and advanced packaging. She also has expertise in physical design and procurement management of 3rd party IP. Before joining Microchip, she worked at Microsemi and Vitesse Semiconductor as a design engineer and engineering manager. She earned an MS in semiconductor devices from North Carolina State University.
|
|