| Tuesday, January 24th |
Tuesday, January 24th
08:30-Noon | | Pre-Conference Tutorial A: Chiplet Basics (Pre-Conference Tutorials Track) | | Moderator: Paul Franzon, Professor, North Carolina State UniversityOrganizer: Matt Ouellette, Director Silicon Product Planning, AMD | Speaker(s):
| Speaker: Matthew Ouellette, Director Silicon Product Planning, AMDSpeaker: David Ratchkov, CTO, Anemoi SoftwareSpeaker: Yervant Zorian, Chief Architect/Fellow, SynopsysSpeaker: Gordon Allan, Product Manager, Siemens EDA | Session Description:
| Chiplets allow designers to develop very large chips efficiently at small process dimensions. The idea is to divide the chips into building blocks (or chiplets). They are essentially drop-in pieces, which designers can buy, reuse from previous designs, or obtain from standard libraries. They may come from older process nodes, utilize new technologies (rather than standard CMOS), or include analog, optical, or other peripheral circuits. The problem, of course, is how to combine them (a step called hetereogenous integration). It requires a high-speed interface such as Bunch-of-Wires (BoW) or Universal Chiplet Interface Express (UCIe). Easier said than done, particularly since developers must do power and thermal analysis across devices as well. Chiplets require complex platforms that offer cross-boundary optimization and support partitioning, validation, packaging, integration, and test as well as design. The results are lower manufacturing cost, shorter time-to-market, and better use of resources. The future of chiplets is bright. We will see new platforms, new interfaces, and new approaches to all the development stages. Chiplets are already the way in which all major chip makers have chosen to implement processors, DPUs, AI chips, communications devices, and ASICs.
| | About the Organizer/Moderator: | Paul Franzon is a professor and Director of Graduate Programs at North Carolina State University (NCSU). He is also the Site Director Center for Advanced Electronics through Machine Learning (CAEML). A well-known researcher, he has over 400 published papers in such journals as IEEE Transactions on VLSI Systems, IEEE Transactions on Circuits and Systems, and IEEE Electron Device Letters and at important conferences such as ECTC, 3DIC, IEDM, ICCAD, EPEPS, and SOCC. He has also written books and contributed chapters to them. Before joining the NCSU faculty, he worked at AT&T Bell Laboratories and Australia Telecom. He has also founded four technology companies. He earned a PhD from the University of Adelaide (Adelaide, Australia). He is an IEEE Fellow and has received many research and teaching awards.
Paul Franzon is a professor and Director of Graduate Programs at North Carolina State University (NCSU). He is also the Site Director Center for Advanced Electronics through Machine Learning (CAEML). A well-known researcher, he has over 400 published papers in such journals as IEEE Transactions on VLSI Systems, IEEE Transactions on Circuits and Systems, and IEEE Electron Device Letters and at important conferences such as ECTC, 3DIC, IEDM, ICCAD, EPEPS, and SOCC. He has also written books and contributed chapters to them. Before joining the NCSU faculty, he worked at AT&T Bell Laboratories and Australia Telecom. He has also founded four technology companies. He earned a PhD from the University of Adelaide (Adelaide, Australia). He is an IEEE Fellow and has received many research and teaching awards.
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Tuesday, January 24th
08:30-Noon | | Pre-Conference Tutorial C: Advanced Packaging Methods (Pre-Conference Tutorials Track) | | Moderator: Adam Cron, Distinguished Architect, SynopsysOrganizer: Lihong Cao, Director Engineering, ASE Group | Speaker(s):
| Speaker: Larry Zu, President, Sarcina TechnologySpeaker: Lihong Cao, Director Engineering, ASE GroupSpeaker: Lihong Cao, Director Engineering, ASE GroupSpeaker: Craig Bishop, CTO, DecaSpeaker: Sam Salama, CEO, Hyperion | Session Description:
| The days of simply selecting a chip package from a few common alternatives are over. Designers using chiplets must integrate package design with chip design and integration. They must have tools that consider packaging throughout the design process, so they can optimize cost, throughput, and heat and power factors over all stages. The goal is a one-stop shop providing heterogeneous integration that will drive faster time-to-market. Packaging can be a major way to add value to the ultimate product and meet the needs of system-level users.
| | About the Organizer/Moderator: | Adam Cron is a Distinguished Architect at Synopsys, where he works on test and security tools for digital ICs. Before joining Synopsys, he held test-related positions at Motorola and Texas Instruments. He has helped architect design-for-test, design- for-manufacturing, and security tools for several generations of products. He chairs IEEE 1838 for 3D-IC test access, and is the editor of IEEE P1149.4 for a mixed-signal test bus. He is also chairing a working group to create a Rest API for MITRE's CWE (Common Weakness Enumeration) and CAPEC (Common Attack Pattern Enumeration and Classification) security databases. Adam is an IEEE Golden Core recipient for long-standing service to the society, and has authored several papers and book chapters. He is also a frequent presenter and organizer at conferences such as DAC (Design Automation Conference) and ITC (International Test Conference). He earned a BS in computer engineering from Syracuse University.
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Tuesday, January 24th
08:30-Noon | | Pre-Conference Tutorial D: Interfaces (Pre-Conference Tutorials Track) | | Organizer + Moderator: Anu Ramamurthy, Staff Engineer, MicrochipModerator: Anu Ramamurthy, Staff Engineer, Microchip | Speaker(s):
| Panelist: Ramin Farjad, CEO, EliyanPanelist: Atom Watanabe, Research Staff Member, IBMPanelist: Paul Borrill, CEO, DaedaelusPanelist: Gerald Pasdast, Form Factor and Compliance Working Group Chair, UCIe™ ConsortiumPanelist: Ramin Farjad, CEO, EliyanPanelist: Gerald Pasdast, Form Factor and Compliance Working Group Chair, UCIe™ ConsortiumPanelist: Letizia Giuliano, VP Solution Engineering, Alphawave SEMI | Session Description:
| High-speed on-chip interfaces are the key to making the chiplet idea work. High data rates are essential to achieve high performance and avoid high latency. The interfaces also must consume little chip area to avoid reducing the total level of integration, and they must add little to power or thermal budgets. Example buses such as Bunch-of-Wires (BoW) and Universal Chiplet Interface Express (UCIe) are already available. Designers must consider cost, chip area, throughput, and support when deciding which one to use for their specific applications. The interface must be flexible, comprehensive, and easy to integrate with a wide variety of chiplets.
| | About the Organizer/Moderator: | Anu Ramamurthy is a Sr Staff Engineer at Microchip Technology, where she works on heterogeneous integration and advanced packaging. She also has expertise in physical design and procurement management of 3rd party IP. Before joining Microchip, she worked at Microsemi and Vitesse Semiconductor as a design engineer and engineering manager. She earned an MS in semiconductor devices from North Carolina State University.
Anu Ramamurthy is a Sr Staff Engineer at Microchip Technology, where she works on heterogeneous integration and advanced packaging. She also has expertise in physical design and procurement management of 3rd party IP. Before joining Microchip, she worked at Microsemi and Vitesse Semiconductor as a design engineer and engineering manager. She earned an MS in semiconductor devices from North Carolina State University.
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Tuesday, January 24th
01:00-5:00 PM | | Pre-Conference Tutorial E: Design Methods (Pre-Conference Tutorials Track) | | Moderator: Bill Gervasi, Principal Systems Architect, NanteroOrganizer: Tony Mastroianni, Advanced Packaging Solutions Director, Siemens EDA | Speaker(s):
| Speaker: Tony Mastroianni, Advanced Packaging Solutions Director, Siemens Digital Industry SoftwareSpeaker: Mike Li, VP of Engineering & New Products, CorigineSpeaker: Carlos Macian Ruiz, ASIC System Architect, MarvellSpeaker: Kenneth Larsen, Director Product Marketing, SynopsysSpeaker: Tony Mastroianni Intro, Advanced Packaging Solutions Director, Siemens Digital Industry SoftwareSpeaker: David Kruckemyer, Principal Engineer, Ventana Micro Systems | Session Description:
| Designing a chiplet is much like any other IC design, since the designer must balance among the usual power, performance, and area (PPA). However, new issues come into play since the chiplet must fit into the overall chip design, so the designer must focus on interfaces and system-level issues. The interfaces must offer high bandwidth without using much chip area or power. Furthermore, the designer must make the chiplet be a useful citizen. It should serve a general purpose that will allow it to fit into a range of designs and interface neatly with all of them. As chiplets become commonplace, many people will design them for sale or inclusion in libraries.
| | About the Organizer/Moderator: | Bill Gervasi is Principal Systems Architect at Nantero, a developer of carbon-nanotube memory. He has been a chairman of the JEDEC international standards organization working on memory and storage standards for over 25 years. Best known for his key role in the widely used DDR memory standards (DDR3, DDR4, and DDR5), he received the JEDEC Award of Excellence for his dedication to standards development work. He has also been an expert witness and an instructor in memory design. He has presented at many conferences, including Hot Chips, Storage Developer Conference, Flash Memory Summit, International SoC Conference, and the Salishan Conference on High-Speed Computing. He is often quoted in the trade and technical press, including EE Times and other media. He holds 10 patents in memory design. He studied computer science and computer engineering at the University of Portland and the Oregon Graduate Research Center.
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Tuesday, January 24th
01:00-5:00 PM | | Pre-Conference Tutorial F: Power and Thermal (Pre-Conference Tutorials Track) | | Organizer: Andras Vass-Varnai, Portfolio Development Executive, Siemens EDAModerator: Sonia Leon, Sr Principal Engineer, Intel | Speaker(s):
| Speaker: David Ratchkov, CTO, Anemoi SoftwareSpeaker: Andras Vass Varnai, Portfolio Development Executive, Siemens EDASpeaker: Pascal Vivet, Scientific Director, CEA-ListSpeaker: Robert Patti, President, nHanced Semiconductors | Session Description:
| Power and thermals are critical design criteria for chiplets. They must be low enough to allow for use in many applications and in repeated inclusions in designs that need more instances to achieve scalability and performance criteria. Tools are also needed to do power and thermal analyses globally as part of heterogeneous integration. Such analyses must include the interfaces between chiplets as well as the chiplets themselves and interactions among them. Designers must be aware that thermal constraints may limit operating frequencies and usage levels of cores and other facilities.
| | About the Organizer/Moderator: |
Sonia Leon is a Senior Principal Engineer at Intel, where she specializes in 3D-IC system technology co-optimization (STCO) and design technology pathfinding. She has technical expertise in advanced silicon technologies across foundries (5nm), including architecture definition, product target setting, foundry selection, circuit design, memories, analog, chip integration, design methodology and tools, and product qualification. Before joining Intel, she worked on processor design at Sun Microsystems and Motorola Semiconductor. She has been active at ISSCC as a chair and session organizer. She earned an MSEE at the University of Southern California.
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Tuesday, January 24th
01:00-5:00 PM | | Pre-Conference Tutorial G: Test and Integration (Pre-Conference Tutorials Track) | | Moderator: Nick Ilyadis, Sr. Director of Product Planning, AchronixOrganizer: Joshua Rubin, Sr Engineer, IBM Research | Speaker(s):
| Speaker: Andrei Berar, Sr Director Test Business Development, Amkor TechnologiesSpeaker: Adam Cron, Distinguished Architect, SynopsysSpeaker: Laura Mirkarimi, VP 3D Technologies, Adeia | Session Description:
| Test and integration are critical stages for chiplets. Integration of multiple chiplets into a single chip is a complex process at best, particularly if the chiplets use different process nodes, substrates, or interfaces. It requires new tools and can take a long time. Testing is also difficult, with the chiplet borders being particularly difficult to handle. Several efforts are underway to provide standards that define an open physical and logical die-to-die interface with the aim of creating a marketplace for chiplets. The Open Compute Project’s Open Domain-Specific Architecture (ODSA) is one that has drawn significant attention. The main challenge is enabling greater interoperability between test structures across chiplets and across vendors. Recent developments have shown promising results. There are also advances in incorporating design-for-test methods into the chiplet development process.
| | About the Organizer/Moderator: | Nick Ilyadis is Senior Director of Product Planning at Achronix, where he oversees all aspects of product planning from concept through production. Nick has 35 years of data and semiconductor engineering and manufacturing experience and holds 72 issued patents. A recognized expert on software and hardware development and quality control, he was previously VP Portfolio/Technology Strategy at Marvell Semiconductor and VP/Group CTO at Broadcom. He has extensive domain knowledge across semiconductors, networking, 5G, data centers, and automotive applications. He earned an MSEE in VLSI Technology from the University of New Hampshire. Nick has been active in many industry groups including the Ethernet Alliance and has participated in many conferences including HP Discover, OFC, Infocom, and Ethernet Technology Summit.
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Tuesday, January 24th
01:00-5:00 PM | | Pre-Conference Tutorial H: The New Open Chiplet Economy (Pre-Conference Tutorials Track) | | Organizer + Moderator: Cliff Grossner, VP Market Intelligence, Open Compute ProjectModerator: Tom Hackenberg, Principal Analyst, Yole IntelligenceOrganizer: Bapi Vinnakota, ODSA Project Lead, Open Compute Project | Speaker(s):
| Speaker: Scott Best, Technical Director, RambusSpeaker: Sid Sheth, CEO, d-MatrixPanelist: Bapi Vinnakota, ODSA Project Lead, Open Compute ProjectSpeaker: John Shalf, Department Head, Lawrence Berkeley National LaboratorySpeaker: Kash Johal, VP of Sales, eTopusSpeaker: Dharmesh Jani, Open Source Ecosystem Leader, MetaSpeaker: James Wong, CTO, Palo Alto ElectronPresenter: Bapi Vinnakota, ODSA Project Lead, Open Compute ProjectSpeaker: Elad Alon, CEO & Co-founder, Blue Cheetah Analog DesignSpeaker: Amber Huffman, Lead Technologist, GoogleSpeaker: Jayaprakash Balachandran, Signal Integrity Engineer, Cisco Systems | Session Description:
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| | About the Organizer/Moderator: | Cliff Grossner is Vice President Market Intelligence & Innovation at the Open Compute Project Foundation, where he leads market intelligence and drives awareness of OCP, establishes training and certification programs, and guides inventors in presenting early-stage company ideas to investors. Cliff is also active in OCP’s Future Technologies Initiative. Before joining OCP, he headed the Cloud and Data Research Practice at Omdia, where he focused on overall research quality and worked on programs in cloud services, data center compute and networking, and data center infrastructure. He previously held senior positions at Alcatel-Lucent, Bell Labs, and Nortel. He earned his PhD at McGill University (Canada) and holds over 10 patents in networking and telecommunications.
Tom Hackenberg is Principal Analyst for Computing and Semiconductors at Yole Intelligence, a division of Yole Group. He works on analyzing processor market trends related to the growing demand for IoT, edge computing, artificial intelligence, and other emerging technologies. He develops processor market monitors and conducts research into related technology trends. He is an industry leader reporting on processor elements including CPUs, MPUs, MCUs, DSPs, SoCs, GPUs, accelerators, FPGAs, and configurable processors. He was previously an analyst for Omdia, IHS Markit, and IMS Research, where he focused on processor market trends. He earned a BS in electrical and computer engineering from University of Texas at Austin.
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Tuesday, January 24th
05:00-6:00 PM | | Superpanel: Successful Co-Package Design in a Post-Moore Era (Panel Track) | | Moderator: Jan Vardaman, President, TechSearch International | Panel Members:
| Panelist: Brett Wilkerson, Product Development Engineer, AMDPanelist: Marcus Pan, Program Manager, Semiconductor Research Corporation (SRC)Panelist: John Ferguson, Director Product Management, Siemens EDAPanelist: Paul Franzon, Professor, North Carolina State UniversityPanelist: Bob Patti, CEO, nHanced Semiconductors | Session Description:
| The next design node is already seeing wide use of chiplets with all major chip makers adopting them. Is this break-it-apart and put-it-back-together approach a winner? Will we reduce design time and cost or are we moving the effort into the new integration stage? Do some heterogeneous integration methods work much better than others? How do designers find the best options for their applications? Will test costs explode or can we control them with a design-for-test strategy? Where does hybrid bonding fit into the design and what are the limitations? Are co-design and co-optimization the keys to the kingdom? How do we define a strategy that will lead to success in the post Moore’s Law world?
| | About the Organizer/Moderator: | Jan Vardaman is president and founder of TechSearch International, a leading source of market research and technology trend analysis in semiconductor packaging since 1987. She is co-author of the book How to Make IC Packages, a columnist with Printed Circuit Design and Fab/Circuits Assembly magazines, and the author of many publications on trends in semiconductor packaging and assembly. She is well-known as a catalyst at conferences, bringing together industry leaders to enlighten attendees about important advances, key companies, and major challenges. She is a senior member of the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society and an IEEE CPMT Distinguished Lecturer. She earned an MS in economics from the University of Texas at Austin.
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Tuesday, January 24th
06:00-8:30 PM | | Chat with the Experts (sponsored by Achronix) (Pre-Conference Tutorials Track) | | Expert Table Leaders:
| Business Issues
Rohit Mittal, Engineering Manager, GoogleStandards
Bapi Vinnakota, System Architect, BroadcomData Management
Michael Munsey, Sr Director Semiconductor/IP Solutions, Siemens EDAIntellectual Property
Letizia Giuliano, VP Solution Engineering, Alphawave SEMIMick Posner,
Product Line Sr Group Director,
Synopsys
Drop-In Chiplets
Nick Ilyadis, Sr. Director of Product Planning, AchronixSecurity
Scott Best, Technical Director, RambusAdam Cron,
Distinguished Architect,
Synopsys
Open Marketplaces
James Wong, CTO, Palo Alto ElectronIntegration
Anu Ramamurthy, Staff Engineer, MicrochipEmulation
Mike Shei, Co-VP R&D, CorigineTom De Schutter,
VP System Solutions,
Synopsys
Partitioning (Disaggregation)
Denis Dutoit, Sr Project Coordinator, CEA-ListFoundry Issues
Kevin Yee, Director IP Marketing, Samsung SemiconductorInterfaces
Jen-Tai Hsu, VP IP Engineering, Global UnichipManmeet Walia,
Director Product Marketing,
Synopsys
Power Issues
Andras Vass-Varnai, Portfolio Development Executive, Siemens EDAEDA Tools
Tony Mastroianni, Advanced Packaging Solutions Director, Siemens Digital Industry SoftwareDesign-for-Test (DFT)
Rajesh Pendurkar, Director, CapgeminiManufacturing Costs
Cliff Sandstrom, VP Technology/Development, Deca TechnologiesHigh Performance Applications
John Shalf, Department Head, Lawrence Berkeley National LaboratoryMemory
Tom Coughlin, President, Coughlin AssociatesUCIe
Gerald Pasdast, Form Factor and Compliance Working Group Chair, UCIe™ ConsortiumOptics
Jeff Hutchins, Director Optical Technology, CTO Office, RanovusSteve Kotowski,
Engineer,
Ayar Labs
Market Research
Tom Hackenberg, Principal Analyst, Yole DevelopmentPackaging
Laura Mirkarimi, VP 3D Technologies, XperiMonitoring
Marc Hutner, Sr Director Product Marketing, proteanTecsYervant Zorian,
Chief Architect/Fellow,
Synopsys
ASICs
Carlos Macian Ruiz, ASIC System Architect, MarvellVenture Capital
Laura Swan, VP of Business Operations,, Silicon Catalyst AngelsArchitectures
Firooz Massoudi, Hardware Architect, SynopsysChiplet Summit 2024
Chuck Sobey, General Chair, Chiplet SummitThermal Issues
Umit Ogras, Associate Professor, University of WisconsinSignal Integrity
Subramanian (Lal) Lalgudi, Analysis/Verification Product Specialist, Siemens EDAAsh Patel,
,
Synopsys
Optimization
Per Viklund, Director IC Packaging, Siemens EDAOpen Chiplet Economy
Nathan Brookwood, Research Fellow, Insight 64Processors
Omar Hassan, Sr VP Business Development, Ventana Micro SystemsTesting
Tim Wooden, Market Development Director, Smiths InterconnectDesign
Pascal Vivet, Scientific Director, CEA-ListShekhar Kapoor,
Sr Director Product Marketing,
Synopsys
| Session Description:
| The Expert Table Leaders Session allows attendees to meet top experts in many crucial areas and ask questions in an informal setting. Each table has a different subject, and attendees are welcome to move from table to table. Subjects will include architectures, design, integration, market research, optimization, packaging, partitioning, platforms. standards, and test. Beer, wine, soft drinks, and pizza will be served to promote the informal atmosphere and encourage networking. Emphasis will be on frequently asked questions, best practices, hints and warnings, major issues, and key products and industry organizations.
| | About the Organizer/Moderator: | |
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